sun4m: Add Sun CG3 framebuffer and corresponding OpenBIOS FCode ROM
The CG3 framebuffer is a simple 8-bit framebuffer for use with operating systems such as early Solaris that do not have drivers for TCX. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> CC: Blue Swirl <blauwirbel@gmail.com> CC: Anthony Liguori <aliguori@amazon.com> CC: Peter Maydell <peter.maydell@linaro.org> CC: Bob Breuer <breuerr@mc.net> CC: Artyom Tarasenko <atar4qemu@gmail.com>
This commit is contained in:
Mark Cave-Ayland
parent
ead4cf04f8
commit
9eb08a435a
2
Makefile
2
Makefile
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@ -319,7 +319,7 @@ ifdef INSTALL_BLOBS
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BLOBS=bios.bin bios-256k.bin sgabios.bin vgabios.bin vgabios-cirrus.bin \
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vgabios-stdvga.bin vgabios-vmware.bin vgabios-qxl.bin \
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acpi-dsdt.aml q35-acpi-dsdt.aml \
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ppc_rom.bin openbios-sparc32 openbios-sparc64 openbios-ppc QEMU,tcx.bin \
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ppc_rom.bin openbios-sparc32 openbios-sparc64 openbios-ppc QEMU,tcx.bin QEMU,cgthree.bin \
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pxe-e1000.rom pxe-eepro100.rom pxe-ne2k_pci.rom \
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pxe-pcnet.rom pxe-rtl8139.rom pxe-virtio.rom \
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efi-e1000.rom efi-eepro100.rom efi-ne2k_pci.rom \
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@ -10,6 +10,7 @@ CONFIG_EMPTY_SLOT=y
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CONFIG_PCNET_COMMON=y
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CONFIG_LANCE=y
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CONFIG_TCX=y
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CONFIG_CG3=y
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CONFIG_SLAVIO=y
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CONFIG_CS4231=y
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CONFIG_GRLIB=y
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@ -28,6 +28,7 @@ obj-$(CONFIG_OMAP) += omap_lcdc.o
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obj-$(CONFIG_PXA2XX) += pxa2xx_lcd.o
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obj-$(CONFIG_SM501) += sm501.o
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obj-$(CONFIG_TCX) += tcx.o
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obj-$(CONFIG_CG3) += cg3.o
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obj-$(CONFIG_VGA) += vga.o
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@ -0,0 +1,385 @@
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/*
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* QEMU CG3 Frame buffer
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*
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* Copyright (c) 2012 Bob Breuer
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* Copyright (c) 2013 Mark Cave-Ayland
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu-common.h"
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#include "qemu/error-report.h"
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#include "ui/console.h"
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#include "hw/sysbus.h"
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#include "hw/loader.h"
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/* Change to 1 to enable debugging */
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#define DEBUG_CG3 0
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#define CG3_ROM_FILE "QEMU,cgthree.bin"
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#define FCODE_MAX_ROM_SIZE 0x10000
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#define CG3_REG_SIZE 0x20
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#define CG3_REG_BT458_ADDR 0x0
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#define CG3_REG_BT458_COLMAP 0x4
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#define CG3_REG_FBC_CTRL 0x10
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#define CG3_REG_FBC_STATUS 0x11
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#define CG3_REG_FBC_CURSTART 0x12
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#define CG3_REG_FBC_CUREND 0x13
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#define CG3_REG_FBC_VCTRL 0x14
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/* Control register flags */
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#define CG3_CR_ENABLE_INTS 0x80
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/* Status register flags */
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#define CG3_SR_PENDING_INT 0x80
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#define CG3_SR_1152_900_76_B 0x60
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#define CG3_SR_ID_COLOR 0x01
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#define CG3_VRAM_SIZE 0x100000
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#define CG3_VRAM_OFFSET 0x800000
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#define DPRINTF(fmt, ...) do { \
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if (DEBUG_CG3) { \
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printf("CG3: " fmt , ## __VA_ARGS__); \
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} \
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} while (0);
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#define TYPE_CG3 "cgthree"
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#define CG3(obj) OBJECT_CHECK(CG3State, (obj), TYPE_CG3)
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typedef struct CG3State {
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SysBusDevice parent_obj;
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QemuConsole *con;
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qemu_irq irq;
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hwaddr prom_addr;
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MemoryRegion vram_mem;
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MemoryRegion rom;
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MemoryRegion reg;
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uint32_t vram_size;
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int full_update;
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uint8_t regs[16];
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uint8_t r[256], g[256], b[256];
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uint16_t width, height, depth;
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uint8_t dac_index, dac_state;
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} CG3State;
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static void cg3_update_display(void *opaque)
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{
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CG3State *s = opaque;
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DisplaySurface *surface = qemu_console_surface(s->con);
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const uint8_t *pix;
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uint32_t *data;
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uint32_t dval;
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int x, y, y_start;
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unsigned int width, height;
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ram_addr_t page, page_min, page_max;
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if (surface_bits_per_pixel(surface) != 32) {
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return;
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}
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width = s->width;
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height = s->height;
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y_start = -1;
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page_min = -1;
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page_max = 0;
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page = 0;
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pix = memory_region_get_ram_ptr(&s->vram_mem);
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data = (uint32_t *)surface_data(surface);
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for (y = 0; y < height; y++) {
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int update = s->full_update;
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page = (y * width) & TARGET_PAGE_MASK;
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update |= memory_region_get_dirty(&s->vram_mem, page, page + width,
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DIRTY_MEMORY_VGA);
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if (update) {
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if (y_start < 0) {
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y_start = y;
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}
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if (page < page_min) {
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page_min = page;
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}
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if (page > page_max) {
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page_max = page;
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}
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for (x = 0; x < width; x++) {
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dval = *pix++;
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dval = (s->r[dval] << 16) | (s->g[dval] << 8) | s->b[dval];
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*data++ = dval;
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}
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} else {
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if (y_start >= 0) {
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dpy_gfx_update(s->con, 0, y_start, s->width, y - y_start);
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y_start = -1;
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}
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pix += width;
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data += width;
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}
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}
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s->full_update = 0;
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if (y_start >= 0) {
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dpy_gfx_update(s->con, 0, y_start, s->width, y - y_start);
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}
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if (page_max >= page_min) {
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memory_region_reset_dirty(&s->vram_mem,
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page_min, page_max - page_min + TARGET_PAGE_SIZE,
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DIRTY_MEMORY_VGA);
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}
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/* vsync interrupt? */
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if (s->regs[0] & CG3_CR_ENABLE_INTS) {
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s->regs[1] |= CG3_SR_PENDING_INT;
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qemu_irq_raise(s->irq);
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}
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}
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static void cg3_invalidate_display(void *opaque)
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{
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CG3State *s = opaque;
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memory_region_set_dirty(&s->vram_mem, 0, CG3_VRAM_SIZE);
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}
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static uint64_t cg3_reg_read(void *opaque, hwaddr addr, unsigned size)
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{
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CG3State *s = opaque;
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int val;
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switch (addr) {
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case CG3_REG_BT458_ADDR:
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case CG3_REG_BT458_COLMAP:
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val = 0;
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break;
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case CG3_REG_FBC_CTRL:
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val = s->regs[0];
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break;
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case CG3_REG_FBC_STATUS:
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/* monitor ID 6, board type = 1 (color) */
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val = s->regs[1] | CG3_SR_1152_900_76_B | CG3_SR_ID_COLOR;
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break;
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case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE:
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val = s->regs[addr - 0x10];
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break;
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default:
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qemu_log_mask(LOG_UNIMP,
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"cg3: Unimplemented register read "
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"reg 0x%" HWADDR_PRIx " size 0x%x\n",
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addr, size);
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val = 0;
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break;
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}
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DPRINTF("read %02x from reg %" HWADDR_PRIx "\n", val, addr);
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return val;
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}
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static void cg3_reg_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned size)
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{
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CG3State *s = opaque;
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uint8_t regval;
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int i;
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DPRINTF("write %" PRIx64 " to reg %" HWADDR_PRIx " size %d\n",
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val, addr, size);
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switch (addr) {
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case CG3_REG_BT458_ADDR:
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s->dac_index = val;
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s->dac_state = 0;
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break;
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case CG3_REG_BT458_COLMAP:
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/* This register can be written to as either a long word or a byte */
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if (size == 1) {
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val <<= 24;
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}
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for (i = 0; i < size; i++) {
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regval = val >> 24;
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switch (s->dac_state) {
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case 0:
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s->r[s->dac_index] = regval;
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s->dac_state++;
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break;
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case 1:
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s->g[s->dac_index] = regval;
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s->dac_state++;
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break;
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case 2:
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s->b[s->dac_index] = regval;
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/* Index autoincrement */
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s->dac_index = (s->dac_index + 1) & 0xff;
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default:
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s->dac_state = 0;
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break;
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}
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val <<= 8;
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}
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s->full_update = 1;
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break;
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case CG3_REG_FBC_CTRL:
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s->regs[0] = val;
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break;
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case CG3_REG_FBC_STATUS:
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if (s->regs[1] & CG3_SR_PENDING_INT) {
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/* clear interrupt */
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s->regs[1] &= ~CG3_SR_PENDING_INT;
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qemu_irq_lower(s->irq);
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}
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break;
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case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE:
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s->regs[addr - 0x10] = val;
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break;
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default:
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qemu_log_mask(LOG_UNIMP,
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"cg3: Unimplemented register write "
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"reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n",
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addr, size, val);
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break;
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}
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}
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static const MemoryRegionOps cg3_reg_ops = {
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.read = cg3_reg_read,
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.write = cg3_reg_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 4,
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},
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};
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static const GraphicHwOps cg3_ops = {
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.invalidate = cg3_invalidate_display,
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.gfx_update = cg3_update_display,
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};
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static void cg3_realizefn(DeviceState *dev, Error **errp)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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CG3State *s = CG3(dev);
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int ret;
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char *fcode_filename;
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/* FCode ROM */
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memory_region_init_ram(&s->rom, NULL, "cg3.prom", FCODE_MAX_ROM_SIZE);
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vmstate_register_ram_global(&s->rom);
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memory_region_set_readonly(&s->rom, true);
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sysbus_init_mmio(sbd, &s->rom);
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fcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, CG3_ROM_FILE);
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if (fcode_filename) {
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ret = load_image_targphys(fcode_filename, s->prom_addr,
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FCODE_MAX_ROM_SIZE);
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if (ret < 0 || ret > FCODE_MAX_ROM_SIZE) {
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error_report("cg3: could not load prom '%s'", CG3_ROM_FILE);
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}
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}
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memory_region_init_io(&s->reg, NULL, &cg3_reg_ops, s, "cg3.reg",
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CG3_REG_SIZE);
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sysbus_init_mmio(sbd, &s->reg);
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memory_region_init_ram(&s->vram_mem, NULL, "cg3.vram", s->vram_size);
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vmstate_register_ram_global(&s->vram_mem);
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sysbus_init_mmio(sbd, &s->vram_mem);
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sysbus_init_irq(sbd, &s->irq);
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s->con = graphic_console_init(DEVICE(dev), &cg3_ops, s);
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qemu_console_resize(s->con, s->width, s->height);
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}
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static int vmstate_cg3_post_load(void *opaque, int version_id)
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{
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CG3State *s = opaque;
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cg3_invalidate_display(s);
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return 0;
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}
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static const VMStateDescription vmstate_cg3 = {
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.name = "cg3",
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.version_id = 1,
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.minimum_version_id = 1,
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.post_load = vmstate_cg3_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT16(height, CG3State),
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VMSTATE_UINT16(width, CG3State),
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VMSTATE_UINT16(depth, CG3State),
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VMSTATE_BUFFER(r, CG3State),
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VMSTATE_BUFFER(g, CG3State),
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VMSTATE_BUFFER(b, CG3State),
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VMSTATE_UINT8(dac_index, CG3State),
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VMSTATE_UINT8(dac_state, CG3State),
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VMSTATE_END_OF_LIST()
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}
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};
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static void cg3_reset(DeviceState *d)
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{
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CG3State *s = CG3(d);
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/* Initialize palette */
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memset(s->r, 0, 256);
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memset(s->g, 0, 256);
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memset(s->b, 0, 256);
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s->dac_state = 0;
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s->full_update = 1;
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qemu_irq_lower(s->irq);
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}
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static Property cg3_properties[] = {
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DEFINE_PROP_UINT32("vram-size", CG3State, vram_size, -1),
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DEFINE_PROP_UINT16("width", CG3State, width, -1),
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DEFINE_PROP_UINT16("height", CG3State, height, -1),
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DEFINE_PROP_UINT16("depth", CG3State, depth, -1),
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DEFINE_PROP_UINT64("prom-addr", CG3State, prom_addr, -1),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void cg3_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = cg3_realizefn;
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dc->reset = cg3_reset;
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dc->vmsd = &vmstate_cg3;
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dc->props = cg3_properties;
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}
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static const TypeInfo cg3_info = {
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.name = TYPE_CG3,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(CG3State),
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.class_init = cg3_class_init,
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};
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static void cg3_register_types(void)
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{
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type_register_static(&cg3_info);
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}
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type_init(cg3_register_types)
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Binary file not shown.
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@ -11,8 +11,8 @@
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firmware implementation. The goal is to implement a 100% IEEE
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1275-1994 (referred to as Open Firmware) compliant firmware.
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The included images for PowerPC (for 32 and 64 bit PPC CPUs),
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Sparc32 (including QEMU,tcx.bin) and Sparc64 are built from OpenBIOS SVN
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revision 1246.
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Sparc32 (including QEMU,tcx.bin and QEMU,cgthree.bin) and Sparc64 are built
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from OpenBIOS SVN revision 1246.
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- SLOF (Slimline Open Firmware) is a free IEEE 1275 Open Firmware
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implementation for certain IBM POWER hardware. The sources are at
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