cpu-exec: prepare for user and softmmu split
There is little in common with user and softmmu versions of cpu_resume_signal(), split them. Fix coding style for the user emulator part. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl
parent
aa29141d84
commit
9eff14f3d5
293
cpu-exec.c
293
cpu-exec.c
@ -64,21 +64,31 @@ void cpu_loop_exit(void)
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/* exit the current TB from a signal handler. The host registers are
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restored in a state compatible with the CPU emulator
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*/
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#if defined(CONFIG_SOFTMMU)
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void cpu_resume_from_signal(CPUState *env1, void *puc)
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{
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env = env1;
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/* XXX: restore cpu registers saved in host registers */
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env->exception_index = -1;
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longjmp(env->jmp_env, 1);
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}
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#else
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void cpu_resume_from_signal(CPUState *env1, void *puc)
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{
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#if !defined(CONFIG_SOFTMMU)
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#ifdef __linux__
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struct ucontext *uc = puc;
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#elif defined(__OpenBSD__)
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struct sigcontext *uc = puc;
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#endif
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#endif
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env = env1;
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/* XXX: restore cpu registers saved in host registers */
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#if !defined(CONFIG_SOFTMMU)
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if (puc) {
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/* XXX: use siglongjmp ? */
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#ifdef __linux__
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@ -91,10 +101,10 @@ void cpu_resume_from_signal(CPUState *env1, void *puc)
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sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL);
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#endif
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}
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#endif
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env->exception_index = -1;
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longjmp(env->jmp_env, 1);
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}
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#endif
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/* Execute the code without caching the generated code. An interpreter
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could be used if available. */
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@ -751,9 +761,11 @@ void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32)
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#if !defined(CONFIG_SOFTMMU)
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#if defined(TARGET_I386)
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#define EXCEPTION_ACTION raise_exception_err(env->exception_index, env->error_code)
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#define EXCEPTION_ACTION \
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raise_exception_err(env->exception_index, env->error_code)
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#else
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#define EXCEPTION_ACTION cpu_loop_exit()
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#define EXCEPTION_ACTION \
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cpu_loop_exit()
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#endif
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/* 'pc' is the host PC at which the exception was raised. 'address' is
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@ -767,8 +779,9 @@ static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
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TranslationBlock *tb;
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int ret;
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if (cpu_single_env)
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if (cpu_single_env) {
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env = cpu_single_env; /* XXX: find a correct solution for multithread */
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}
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#if defined(DEBUG_SIGNAL)
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qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
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pc, address, is_write, *(unsigned long *)old_set);
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@ -780,10 +793,12 @@ static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
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/* see if it is an MMU fault */
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ret = cpu_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
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if (ret < 0)
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if (ret < 0) {
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return 0; /* not an MMU fault */
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if (ret == 0)
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}
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if (ret == 0) {
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return 1; /* the MMU fault was handled without causing real CPU fault */
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}
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/* now we have a real cpu fault */
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tb = tb_find_pc(pc);
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if (tb) {
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@ -804,43 +819,43 @@ static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
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#if defined(__i386__)
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#if defined(__APPLE__)
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# include <sys/ucontext.h>
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#include <sys/ucontext.h>
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# define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
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# define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
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# define ERROR_sig(context) ((context)->uc_mcontext->es.err)
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# define MASK_sig(context) ((context)->uc_sigmask)
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#elif defined (__NetBSD__)
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# include <ucontext.h>
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#define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext->ss.eip))
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#define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
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#define ERROR_sig(context) ((context)->uc_mcontext->es.err)
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#define MASK_sig(context) ((context)->uc_sigmask)
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#elif defined(__NetBSD__)
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#include <ucontext.h>
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# define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP])
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# define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
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# define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
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# define MASK_sig(context) ((context)->uc_sigmask)
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#elif defined (__FreeBSD__) || defined(__DragonFly__)
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# include <ucontext.h>
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#define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP])
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#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
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#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
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#define MASK_sig(context) ((context)->uc_sigmask)
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#elif defined(__FreeBSD__) || defined(__DragonFly__)
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#include <ucontext.h>
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# define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext.mc_eip))
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# define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
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# define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
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# define MASK_sig(context) ((context)->uc_sigmask)
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#define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_eip))
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#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
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#define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
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#define MASK_sig(context) ((context)->uc_sigmask)
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#elif defined(__OpenBSD__)
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# define EIP_sig(context) ((context)->sc_eip)
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# define TRAP_sig(context) ((context)->sc_trapno)
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# define ERROR_sig(context) ((context)->sc_err)
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# define MASK_sig(context) ((context)->sc_mask)
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#define EIP_sig(context) ((context)->sc_eip)
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#define TRAP_sig(context) ((context)->sc_trapno)
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#define ERROR_sig(context) ((context)->sc_err)
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#define MASK_sig(context) ((context)->sc_mask)
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#else
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# define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
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# define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
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# define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
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# define MASK_sig(context) ((context)->uc_sigmask)
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#define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
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#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
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#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
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#define MASK_sig(context) ((context)->uc_sigmask)
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#endif
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int cpu_signal_handler(int host_signum, void *pinfo,
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void *puc)
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{
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siginfo_t *info = pinfo;
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#if defined(__NetBSD__) || defined (__FreeBSD__) || defined(__DragonFly__)
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#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
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ucontext_t *uc = puc;
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#elif defined(__OpenBSD__)
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struct sigcontext *uc = puc;
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@ -876,10 +891,10 @@ int cpu_signal_handler(int host_signum, void *pinfo,
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#define TRAP_sig(context) ((context)->sc_trapno)
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#define ERROR_sig(context) ((context)->sc_err)
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#define MASK_sig(context) ((context)->sc_mask)
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#elif defined (__FreeBSD__) || defined(__DragonFly__)
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#elif defined(__FreeBSD__) || defined(__DragonFly__)
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#include <ucontext.h>
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#define PC_sig(context) (*((unsigned long*)&(context)->uc_mcontext.mc_rip))
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#define PC_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_rip))
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#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
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#define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
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#define MASK_sig(context) ((context)->uc_sigmask)
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@ -895,7 +910,7 @@ int cpu_signal_handler(int host_signum, void *pinfo,
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{
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siginfo_t *info = pinfo;
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unsigned long pc;
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#if defined(__NetBSD__) || defined (__FreeBSD__) || defined(__DragonFly__)
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#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
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ucontext_t *uc = puc;
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#elif defined(__OpenBSD__)
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struct sigcontext *uc = puc;
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@ -918,61 +933,84 @@ int cpu_signal_handler(int host_signum, void *pinfo,
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*/
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#ifdef linux
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/* All Registers access - only for local access */
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# define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
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#define REG_sig(reg_name, context) \
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((context)->uc_mcontext.regs->reg_name)
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/* Gpr Registers access */
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# define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
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# define IAR_sig(context) REG_sig(nip, context) /* Program counter */
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# define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
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# define CTR_sig(context) REG_sig(ctr, context) /* Count register */
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# define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
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# define LR_sig(context) REG_sig(link, context) /* Link register */
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# define CR_sig(context) REG_sig(ccr, context) /* Condition register */
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#define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
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/* Program counter */
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#define IAR_sig(context) REG_sig(nip, context)
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/* Machine State Register (Supervisor) */
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#define MSR_sig(context) REG_sig(msr, context)
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/* Count register */
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#define CTR_sig(context) REG_sig(ctr, context)
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/* User's integer exception register */
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#define XER_sig(context) REG_sig(xer, context)
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/* Link register */
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#define LR_sig(context) REG_sig(link, context)
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/* Condition register */
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#define CR_sig(context) REG_sig(ccr, context)
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/* Float Registers access */
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# define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
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# define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
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#define FLOAT_sig(reg_num, context) \
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(((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num])
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#define FPSCR_sig(context) \
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(*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4)))
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/* Exception Registers access */
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# define DAR_sig(context) REG_sig(dar, context)
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# define DSISR_sig(context) REG_sig(dsisr, context)
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# define TRAP_sig(context) REG_sig(trap, context)
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#define DAR_sig(context) REG_sig(dar, context)
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#define DSISR_sig(context) REG_sig(dsisr, context)
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#define TRAP_sig(context) REG_sig(trap, context)
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#endif /* linux */
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#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
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#include <ucontext.h>
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# define IAR_sig(context) ((context)->uc_mcontext.mc_srr0)
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# define MSR_sig(context) ((context)->uc_mcontext.mc_srr1)
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# define CTR_sig(context) ((context)->uc_mcontext.mc_ctr)
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# define XER_sig(context) ((context)->uc_mcontext.mc_xer)
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# define LR_sig(context) ((context)->uc_mcontext.mc_lr)
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# define CR_sig(context) ((context)->uc_mcontext.mc_cr)
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#define IAR_sig(context) ((context)->uc_mcontext.mc_srr0)
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#define MSR_sig(context) ((context)->uc_mcontext.mc_srr1)
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#define CTR_sig(context) ((context)->uc_mcontext.mc_ctr)
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#define XER_sig(context) ((context)->uc_mcontext.mc_xer)
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#define LR_sig(context) ((context)->uc_mcontext.mc_lr)
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#define CR_sig(context) ((context)->uc_mcontext.mc_cr)
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/* Exception Registers access */
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# define DAR_sig(context) ((context)->uc_mcontext.mc_dar)
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# define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr)
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# define TRAP_sig(context) ((context)->uc_mcontext.mc_exc)
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#define DAR_sig(context) ((context)->uc_mcontext.mc_dar)
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#define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr)
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#define TRAP_sig(context) ((context)->uc_mcontext.mc_exc)
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#endif /* __FreeBSD__|| __FreeBSD_kernel__ */
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#ifdef __APPLE__
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# include <sys/ucontext.h>
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#include <sys/ucontext.h>
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typedef struct ucontext SIGCONTEXT;
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/* All Registers access - only for local access */
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# define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
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# define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
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# define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
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# define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
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#define REG_sig(reg_name, context) \
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((context)->uc_mcontext->ss.reg_name)
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#define FLOATREG_sig(reg_name, context) \
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((context)->uc_mcontext->fs.reg_name)
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#define EXCEPREG_sig(reg_name, context) \
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((context)->uc_mcontext->es.reg_name)
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#define VECREG_sig(reg_name, context) \
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((context)->uc_mcontext->vs.reg_name)
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/* Gpr Registers access */
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# define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
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# define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
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# define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
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# define CTR_sig(context) REG_sig(ctr, context)
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# define XER_sig(context) REG_sig(xer, context) /* Link register */
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# define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
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# define CR_sig(context) REG_sig(cr, context) /* Condition register */
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#define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
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/* Program counter */
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#define IAR_sig(context) REG_sig(srr0, context)
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/* Machine State Register (Supervisor) */
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#define MSR_sig(context) REG_sig(srr1, context)
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#define CTR_sig(context) REG_sig(ctr, context)
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/* Link register */
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#define XER_sig(context) REG_sig(xer, context)
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/* User's integer exception register */
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#define LR_sig(context) REG_sig(lr, context)
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/* Condition register */
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#define CR_sig(context) REG_sig(cr, context)
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/* Float Registers access */
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# define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
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# define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
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#define FLOAT_sig(reg_num, context) \
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FLOATREG_sig(fpregs[reg_num], context)
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#define FPSCR_sig(context) \
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((double)FLOATREG_sig(fpscr, context))
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/* Exception Registers access */
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# define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
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# define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
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# define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
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/* Fault registers for coredump */
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#define DAR_sig(context) EXCEPREG_sig(dar, context)
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#define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
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/* number of powerpc exception taken */
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#define TRAP_sig(context) EXCEPREG_sig(exception, context)
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#endif /* __APPLE__ */
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int cpu_signal_handler(int host_signum, void *pinfo,
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@ -991,11 +1029,13 @@ int cpu_signal_handler(int host_signum, void *pinfo,
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is_write = 0;
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#if 0
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/* ppc 4xx case */
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if (DSISR_sig(uc) & 0x00800000)
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if (DSISR_sig(uc) & 0x00800000) {
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is_write = 1;
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}
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#else
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if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
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if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) {
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is_write = 1;
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}
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#endif
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return handle_cpu_signal(pc, (unsigned long)info->si_addr,
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is_write, &uc->uc_sigmask, puc);
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@ -1014,18 +1054,18 @@ int cpu_signal_handler(int host_signum, void *pinfo,
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/* XXX: need kernel patch to get write flag faster */
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switch (insn >> 26) {
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case 0x0d: // stw
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case 0x0e: // stb
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case 0x0f: // stq_u
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case 0x24: // stf
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case 0x25: // stg
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case 0x26: // sts
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case 0x27: // stt
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case 0x2c: // stl
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case 0x2d: // stq
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case 0x2e: // stl_c
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case 0x2f: // stq_c
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is_write = 1;
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case 0x0d: /* stw */
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case 0x0e: /* stb */
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case 0x0f: /* stq_u */
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case 0x24: /* stf */
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case 0x25: /* stg */
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case 0x26: /* sts */
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case 0x27: /* stt */
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case 0x2c: /* stl */
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case 0x2d: /* stq */
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case 0x2e: /* stl_c */
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case 0x2f: /* stq_c */
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is_write = 1;
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}
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return handle_cpu_signal(pc, (unsigned long)info->si_addr,
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@ -1060,29 +1100,29 @@ int cpu_signal_handler(int host_signum, void *pinfo,
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is_write = 0;
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insn = *(uint32_t *)pc;
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if ((insn >> 30) == 3) {
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switch((insn >> 19) & 0x3f) {
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case 0x05: // stb
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case 0x15: // stba
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case 0x06: // sth
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case 0x16: // stha
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case 0x04: // st
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case 0x14: // sta
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case 0x07: // std
|
||||
case 0x17: // stda
|
||||
case 0x0e: // stx
|
||||
case 0x1e: // stxa
|
||||
case 0x24: // stf
|
||||
case 0x34: // stfa
|
||||
case 0x27: // stdf
|
||||
case 0x37: // stdfa
|
||||
case 0x26: // stqf
|
||||
case 0x36: // stqfa
|
||||
case 0x25: // stfsr
|
||||
case 0x3c: // casa
|
||||
case 0x3e: // casxa
|
||||
is_write = 1;
|
||||
break;
|
||||
}
|
||||
switch ((insn >> 19) & 0x3f) {
|
||||
case 0x05: /* stb */
|
||||
case 0x15: /* stba */
|
||||
case 0x06: /* sth */
|
||||
case 0x16: /* stha */
|
||||
case 0x04: /* st */
|
||||
case 0x14: /* sta */
|
||||
case 0x07: /* std */
|
||||
case 0x17: /* stda */
|
||||
case 0x0e: /* stx */
|
||||
case 0x1e: /* stxa */
|
||||
case 0x24: /* stf */
|
||||
case 0x34: /* stfa */
|
||||
case 0x27: /* stdf */
|
||||
case 0x37: /* stdfa */
|
||||
case 0x26: /* stqf */
|
||||
case 0x36: /* stqfa */
|
||||
case 0x25: /* stfsr */
|
||||
case 0x3c: /* casa */
|
||||
case 0x3e: /* casxa */
|
||||
is_write = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
||||
is_write, sigmask, NULL);
|
||||
@ -1132,7 +1172,7 @@ int cpu_signal_handler(int host_signum, void *pinfo,
|
||||
|
||||
#ifndef __ISR_VALID
|
||||
/* This ought to be in <bits/siginfo.h>... */
|
||||
# define __ISR_VALID 1
|
||||
# define __ISR_VALID 1
|
||||
#endif
|
||||
|
||||
int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
|
||||
@ -1144,18 +1184,19 @@ int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
|
||||
|
||||
ip = uc->uc_mcontext.sc_ip;
|
||||
switch (host_signum) {
|
||||
case SIGILL:
|
||||
case SIGFPE:
|
||||
case SIGSEGV:
|
||||
case SIGBUS:
|
||||
case SIGTRAP:
|
||||
if (info->si_code && (info->si_segvflags & __ISR_VALID))
|
||||
/* ISR.W (write-access) is bit 33: */
|
||||
is_write = (info->si_isr >> 33) & 1;
|
||||
break;
|
||||
case SIGILL:
|
||||
case SIGFPE:
|
||||
case SIGSEGV:
|
||||
case SIGBUS:
|
||||
case SIGTRAP:
|
||||
if (info->si_code && (info->si_segvflags & __ISR_VALID)) {
|
||||
/* ISR.W (write-access) is bit 33: */
|
||||
is_write = (info->si_isr >> 33) & 1;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return handle_cpu_signal(ip, (unsigned long)info->si_addr,
|
||||
is_write,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user