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riscv: Fix introspection problems

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This is based on Thomas's work fixing introspection problems [1] and
 applied to the RISC-V port.
 
 1: https://lists.gnu.org/archive/html/qemu-devel/2018-07/msg03261.html
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Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-pull-20180719' into staging

riscv: Fix introspection problems

This is based on Thomas's work fixing introspection problems [1] and
applied to the RISC-V port.

1: https://lists.gnu.org/archive/html/qemu-devel/2018-07/msg03261.html

# gpg: Signature made Thu 19 Jul 2018 17:06:07 BST
# gpg:                using RSA key 21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>"
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg:          It is not certain that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-pull-20180719:
  spike: Fix crash when introspecting the device
  riscv_hart: Fix crash when introspecting the device
  virt: Fix crash when introspecting the device
  sifive_u: Fix crash when introspecting the device
  sifive_e: Fix crash when introspecting the device

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2018-07-19 17:21:43 +01:00
commit 9f2b67e1ca
5 changed files with 22 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
hw/riscv/riscv_hart.c
View File

@ -45,11 +45,10 @@ static void riscv_harts_realize(DeviceState *dev, Error **errp)
s->harts = g_new0(RISCVCPU, s->num_harts);
for (n = 0; n < s->num_harts; n++) {
object_initialize(&s->harts[n], sizeof(RISCVCPU), s->cpu_type);
object_initialize_child(OBJECT(s), "harts[*]", &s->harts[n],
sizeof(RISCVCPU), s->cpu_type,
&error_abort, NULL);
s->harts[n].env.mhartid = n;
object_property_add_child(OBJECT(s), "harts[*]", OBJECT(&s->harts[n]),
&error_abort);
qemu_register_reset(riscv_harts_cpu_reset, &s->harts[n]);
object_property_set_bool(OBJECT(&s->harts[n]), true,
"realized", &err);

12
hw/riscv/sifive_e.c
View File

@ -105,9 +105,9 @@ static void riscv_sifive_e_init(MachineState *machine)
int i;
/* Initialize SoC */
object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_E_SOC);
object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
&error_abort);
object_initialize_child(OBJECT(machine), "soc", &s->soc,
sizeof(s->soc), TYPE_RISCV_E_SOC,
&error_abort, NULL);
object_property_set_bool(OBJECT(&s->soc), true, "realized",
&error_abort);
@ -139,9 +139,9 @@ static void riscv_sifive_e_soc_init(Object *obj)
{
SiFiveESoCState *s = RISCV_E_SOC(obj);
object_initialize(&s->cpus, sizeof(s->cpus), TYPE_RISCV_HART_ARRAY);
object_property_add_child(obj, "cpus", OBJECT(&s->cpus),
&error_abort);
object_initialize_child(obj, "cpus", &s->cpus,
sizeof(s->cpus), TYPE_RISCV_HART_ARRAY,
&error_abort, NULL);
object_property_set_str(OBJECT(&s->cpus), SIFIVE_E_CPU, "cpu-type",
&error_abort);
object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts",

15
hw/riscv/sifive_u.c
View File

@ -244,9 +244,9 @@ static void riscv_sifive_u_init(MachineState *machine)
int i;
/* Initialize SoC */
object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_U_SOC);
object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
&error_abort);
object_initialize_child(OBJECT(machine), "soc", &s->soc,
sizeof(s->soc), TYPE_RISCV_U_SOC,
&error_abort, NULL);
object_property_set_bool(OBJECT(&s->soc), true, "realized",
&error_abort);
@ -303,16 +303,15 @@ static void riscv_sifive_u_soc_init(Object *obj)
{
SiFiveUSoCState *s = RISCV_U_SOC(obj);
object_initialize(&s->cpus, sizeof(s->cpus), TYPE_RISCV_HART_ARRAY);
object_property_add_child(obj, "cpus", OBJECT(&s->cpus),
&error_abort);
object_initialize_child(obj, "cpus", &s->cpus, sizeof(s->cpus),
TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
object_property_set_str(OBJECT(&s->cpus), SIFIVE_U_CPU, "cpu-type",
&error_abort);
object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts",
&error_abort);
object_initialize(&s->gem, sizeof(s->gem), TYPE_CADENCE_GEM);
qdev_set_parent_bus(DEVICE(&s->gem), sysbus_get_default());
sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
TYPE_CADENCE_GEM);
}
static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)

10
hw/riscv/spike.c
View File

@ -171,9 +171,8 @@ static void spike_v1_10_0_board_init(MachineState *machine)
int i;
/* Initialize SOC */
object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY);
object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
&error_abort);
object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
object_property_set_str(OBJECT(&s->soc), SPIKE_V1_10_0_CPU, "cpu-type",
&error_abort);
object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
@ -254,9 +253,8 @@ static void spike_v1_09_1_board_init(MachineState *machine)
int i;
/* Initialize SOC */
object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY);
object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
&error_abort);
object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
object_property_set_str(OBJECT(&s->soc), SPIKE_V1_09_1_CPU, "cpu-type",
&error_abort);
object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",

5
hw/riscv/virt.c
View File

@ -274,9 +274,8 @@ static void riscv_virt_board_init(MachineState *machine)
void *fdt;
/* Initialize SOC */
object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY);
object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
&error_abort);
object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
object_property_set_str(OBJECT(&s->soc), VIRT_CPU, "cpu-type",
&error_abort);
object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",