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target-tilegx: Add cpu basic features for linux-user

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It implements minimized cpu features for linux-user.

Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <BLU436-SMTP114819BB03D853801AA9C3CB9660@phx.gbl>
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Chen Gang 2015-08-21 05:41:01 +08:00 committed by Richard Henderson
parent b69773a8a7
commit 9f64170df2
2 changed files with 345 additions and 0 deletions
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/*
* QEMU TILE-Gx CPU
*
* Copyright (c) 2015 Chen Gang
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see
* <http://www.gnu.org/licenses/lgpl-2.1.html>
*/
#include "cpu.h"
#include "qemu-common.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
static void tilegx_cpu_dump_state(CPUState *cs, FILE *f,
fprintf_function cpu_fprintf, int flags)
{
static const char * const reg_names[TILEGX_R_COUNT] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
"r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
"r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
"r48", "r49", "r50", "r51", "bp", "tp", "sp", "lr"
};
TileGXCPU *cpu = TILEGX_CPU(cs);
CPUTLGState *env = &cpu->env;
int i;
for (i = 0; i < TILEGX_R_COUNT; i++) {
cpu_fprintf(f, "%-4s" TARGET_FMT_lx "%s",
reg_names[i], env->regs[i],
(i % 4) == 3 ? "\n" : " ");
}
cpu_fprintf(f, "PC " TARGET_FMT_lx " CEX " TARGET_FMT_lx "\n\n",
env->pc, env->spregs[TILEGX_SPR_CMPEXCH]);
}
TileGXCPU *cpu_tilegx_init(const char *cpu_model)
{
TileGXCPU *cpu;
cpu = TILEGX_CPU(object_new(TYPE_TILEGX_CPU));
object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
return cpu;
}
static void tilegx_cpu_set_pc(CPUState *cs, vaddr value)
{
TileGXCPU *cpu = TILEGX_CPU(cs);
cpu->env.pc = value;
}
static bool tilegx_cpu_has_work(CPUState *cs)
{
return true;
}
static void tilegx_cpu_reset(CPUState *s)
{
TileGXCPU *cpu = TILEGX_CPU(s);
TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(cpu);
CPUTLGState *env = &cpu->env;
tcc->parent_reset(s);
memset(env, 0, sizeof(CPUTLGState));
tlb_flush(s, 1);
}
static void tilegx_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(dev);
cpu_reset(cs);
qemu_init_vcpu(cs);
tcc->parent_realize(dev, errp);
}
static void tilegx_cpu_initfn(Object *obj)
{
CPUState *cs = CPU(obj);
TileGXCPU *cpu = TILEGX_CPU(obj);
CPUTLGState *env = &cpu->env;
static bool tcg_initialized;
cs->env_ptr = env;
cpu_exec_init(cs, &error_abort);
if (tcg_enabled() && !tcg_initialized) {
tcg_initialized = true;
tilegx_tcg_init();
}
}
static void tilegx_cpu_do_interrupt(CPUState *cs)
{
cs->exception_index = -1;
}
static int tilegx_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
int mmu_idx)
{
cpu_dump_state(cs, stderr, fprintf, 0);
return 1;
}
static bool tilegx_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
if (interrupt_request & CPU_INTERRUPT_HARD) {
tilegx_cpu_do_interrupt(cs);
return true;
}
return false;
}
static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
TileGXCPUClass *tcc = TILEGX_CPU_CLASS(oc);
tcc->parent_realize = dc->realize;
dc->realize = tilegx_cpu_realizefn;
tcc->parent_reset = cc->reset;
cc->reset = tilegx_cpu_reset;
cc->has_work = tilegx_cpu_has_work;
cc->do_interrupt = tilegx_cpu_do_interrupt;
cc->cpu_exec_interrupt = tilegx_cpu_exec_interrupt;
cc->dump_state = tilegx_cpu_dump_state;
cc->set_pc = tilegx_cpu_set_pc;
cc->handle_mmu_fault = tilegx_cpu_handle_mmu_fault;
cc->gdb_num_core_regs = 0;
}
static const TypeInfo tilegx_cpu_type_info = {
.name = TYPE_TILEGX_CPU,
.parent = TYPE_CPU,
.instance_size = sizeof(TileGXCPU),
.instance_init = tilegx_cpu_initfn,
.class_size = sizeof(TileGXCPUClass),
.class_init = tilegx_cpu_class_init,
};
static void tilegx_cpu_register_types(void)
{
type_register_static(&tilegx_cpu_type_info);
}
type_init(tilegx_cpu_register_types)

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/*
* TILE-Gx virtual CPU header
*
* Copyright (c) 2015 Chen Gang
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef CPU_TILEGX_H
#define CPU_TILEGX_H
#include "config.h"
#include "qemu-common.h"
#define TARGET_LONG_BITS 64
#define CPUArchState struct CPUTLGState
#include "exec/cpu-defs.h"
/* TILE-Gx common register alias */
#define TILEGX_R_RE 0 /* 0 register, for function/syscall return value */
#define TILEGX_R_ERR 1 /* 1 register, for syscall errno flag */
#define TILEGX_R_NR 10 /* 10 register, for syscall number */
#define TILEGX_R_BP 52 /* 52 register, optional frame pointer */
#define TILEGX_R_TP 53 /* TP register, thread local storage data */
#define TILEGX_R_SP 54 /* SP register, stack pointer */
#define TILEGX_R_LR 55 /* LR register, may save pc, but it is not pc */
#define TILEGX_R_COUNT 56 /* Only 56 registers are really useful */
#define TILEGX_R_SN 56 /* SN register, obsoleted, it likes zero register */
#define TILEGX_R_IDN0 57 /* IDN0 register, cause IDN_ACCESS exception */
#define TILEGX_R_IDN1 58 /* IDN1 register, cause IDN_ACCESS exception */
#define TILEGX_R_UDN0 59 /* UDN0 register, cause UDN_ACCESS exception */
#define TILEGX_R_UDN1 60 /* UDN1 register, cause UDN_ACCESS exception */
#define TILEGX_R_UDN2 61 /* UDN2 register, cause UDN_ACCESS exception */
#define TILEGX_R_UDN3 62 /* UDN3 register, cause UDN_ACCESS exception */
#define TILEGX_R_ZERO 63 /* Zero register, always zero */
#define TILEGX_R_NOREG 255 /* Invalid register value */
/* TILE-Gx special registers used by outside */
enum {
TILEGX_SPR_CMPEXCH = 0,
TILEGX_SPR_CRITICAL_SEC = 1,
TILEGX_SPR_SIM_CONTROL = 2,
TILEGX_SPR_COUNT
};
/* Exception numbers */
typedef enum {
TILEGX_EXCP_NONE = 0,
TILEGX_EXCP_SYSCALL = 1,
TILEGX_EXCP_OPCODE_UNKNOWN = 0x101,
TILEGX_EXCP_OPCODE_UNIMPLEMENTED = 0x102,
TILEGX_EXCP_OPCODE_CMPEXCH = 0x103,
TILEGX_EXCP_OPCODE_CMPEXCH4 = 0x104,
TILEGX_EXCP_OPCODE_EXCH = 0x105,
TILEGX_EXCP_OPCODE_EXCH4 = 0x106,
TILEGX_EXCP_OPCODE_FETCHADD = 0x107,
TILEGX_EXCP_OPCODE_FETCHADD4 = 0x108,
TILEGX_EXCP_OPCODE_FETCHADDGEZ = 0x109,
TILEGX_EXCP_OPCODE_FETCHADDGEZ4 = 0x10a,
TILEGX_EXCP_OPCODE_FETCHAND = 0x10b,
TILEGX_EXCP_OPCODE_FETCHAND4 = 0x10c,
TILEGX_EXCP_OPCODE_FETCHOR = 0x10d,
TILEGX_EXCP_OPCODE_FETCHOR4 = 0x10e,
TILEGX_EXCP_REG_IDN_ACCESS = 0x181,
TILEGX_EXCP_REG_UDN_ACCESS = 0x182,
TILEGX_EXCP_UNALIGNMENT = 0x201,
TILEGX_EXCP_DBUG_BREAK = 0x301
} TileExcp;
typedef struct CPUTLGState {
uint64_t regs[TILEGX_R_COUNT]; /* Common used registers by outside */
uint64_t spregs[TILEGX_SPR_COUNT]; /* Special used registers by outside */
uint64_t pc; /* Current pc */
#if defined(CONFIG_USER_ONLY)
uint32_t excparam; /* exception parameter */
#endif
CPU_COMMON
} CPUTLGState;
#include "qom/cpu.h"
#define TYPE_TILEGX_CPU "tilegx-cpu"
#define TILEGX_CPU_CLASS(klass) \
OBJECT_CLASS_CHECK(TileGXCPUClass, (klass), TYPE_TILEGX_CPU)
#define TILEGX_CPU(obj) \
OBJECT_CHECK(TileGXCPU, (obj), TYPE_TILEGX_CPU)
#define TILEGX_CPU_GET_CLASS(obj) \
OBJECT_GET_CLASS(TileGXCPUClass, (obj), TYPE_TILEGX_CPU)
/**
* TileGXCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
*
* A Tile-Gx CPU model.
*/
typedef struct TileGXCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
void (*parent_reset)(CPUState *cpu);
} TileGXCPUClass;
/**
* TileGXCPU:
* @env: #CPUTLGState
*
* A Tile-GX CPU.
*/
typedef struct TileGXCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUTLGState env;
} TileGXCPU;
static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState *env)
{
return container_of(env, TileGXCPU, env);
}
#define ENV_GET_CPU(e) CPU(tilegx_env_get_cpu(e))
#define ENV_OFFSET offsetof(TileGXCPU, env)
/* TILE-Gx memory attributes */
#define TARGET_PAGE_BITS 16 /* TILE-Gx uses 64KB page size */
#define TARGET_PHYS_ADDR_SPACE_BITS 42
#define TARGET_VIRT_ADDR_SPACE_BITS 64
#define MMU_USER_IDX 0 /* Current memory operation is in user mode */
#include "exec/cpu-all.h"
void tilegx_tcg_init(void);
int cpu_tilegx_exec(CPUState *s);
int cpu_tilegx_signal_handler(int host_signum, void *pinfo, void *puc);
TileGXCPU *cpu_tilegx_init(const char *cpu_model);
#define cpu_init(cpu_model) CPU(cpu_tilegx_init(cpu_model))
#define cpu_exec cpu_tilegx_exec
#define cpu_gen_code cpu_tilegx_gen_code
#define cpu_signal_handler cpu_tilegx_signal_handler
static inline void cpu_get_tb_cpu_state(CPUTLGState *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{
*pc = env->pc;
*cs_base = 0;
*flags = 0;
}
#include "exec/exec-all.h"
#endif