hw/mips/malta: Trace FPGA LEDs/ASCII display updates
The FPGA LEDs/ASCII display is mostly used by the bootloader to show very low-level debug info. QEMU connects its output to a character device backend, which is not very practical to correlate with ASM instruction executed, interrupts or MMIO accesses. Also, the display discard the previous states. To ease bootloader debugging experience, add a pair of trace events. Such events can be analyzed over time or diff-ed between different runs. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230104133935.4639-4-philmd@linaro.org>
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@ -58,6 +58,7 @@
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#include "semihosting/semihost.h"
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#include "hw/mips/cps.h"
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#include "hw/qdev-clock.h"
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#include "trace.h"
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#define ENVP_PADDR 0x2000
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#define ENVP_VADDR cpu_mips_phys_to_kseg0(NULL, ENVP_PADDR)
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@ -120,12 +121,14 @@ static void malta_fpga_update_display_leds(MaltaFPGAState *s)
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}
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leds_text[8] = '\0';
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trace_malta_fpga_leds(leds_text);
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qemu_chr_fe_printf(&s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n",
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leds_text);
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}
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static void malta_fpga_update_display_ascii(MaltaFPGAState *s)
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{
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trace_malta_fpga_display(s->display_text);
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qemu_chr_fe_printf(&s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|",
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s->display_text);
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}
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@ -4,3 +4,7 @@ gt64120_write(uint64_t addr, uint64_t value) "gt64120 write 0x%03"PRIx64" value:
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gt64120_read_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 read %s size:%u value:0x%08" PRIx64
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gt64120_write_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 write %s size:%u value:0x%08" PRIx64
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gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_length, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRIx64 "@0x%08" PRIx64
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# malta.c
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malta_fpga_leds(const char *text) "LEDs %s"
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malta_fpga_display(const char *text) "ASCII '%s'"
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