target-arm: A64: Implement SIMD scalar indexed instructions
Implement the SIMD scalar indexed instructions. The encoding here is nearly identical to the vector indexed grouping, so we combine the two. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Peter Maydell
parent
c44ad1fddc
commit
9f82e0ff4b
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@ -6322,17 +6322,6 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
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}
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}
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/* C3.6.13 AdvSIMD scalar x indexed element
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* 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
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* +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
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* | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
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* +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
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*/
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static void disas_simd_scalar_indexed(DisasContext *s, uint32_t insn)
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{
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unsupported_encoding(s, insn);
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}
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/* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
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static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u,
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int immh, int immb, int opcode, int rn, int rd)
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@ -7805,13 +7794,18 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
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}
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}
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/* C3.6.18 AdvSIMD vector x indexed element
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/* C3.6.13 AdvSIMD scalar x indexed element
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* 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
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* +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
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* | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
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* +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
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* C3.6.18 AdvSIMD vector x indexed element
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* 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
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* +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
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* | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
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* +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
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*/
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static void disas_simd_indexed_vector(DisasContext *s, uint32_t insn)
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static void disas_simd_indexed(DisasContext *s, uint32_t insn)
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{
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/* This encoding has two kinds of instruction:
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* normal, where we perform elt x idxelt => elt for each
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@ -7820,6 +7814,7 @@ static void disas_simd_indexed_vector(DisasContext *s, uint32_t insn)
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* double the width of the input element
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* The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
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*/
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bool is_scalar = extract32(insn, 28, 1);
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bool is_q = extract32(insn, 30, 1);
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bool u = extract32(insn, 29, 1);
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int size = extract32(insn, 22, 2);
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@ -7839,7 +7834,7 @@ static void disas_simd_indexed_vector(DisasContext *s, uint32_t insn)
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switch (opcode) {
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case 0x0: /* MLA */
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case 0x4: /* MLS */
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if (!u) {
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if (!u || is_scalar) {
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unallocated_encoding(s);
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return;
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}
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@ -7847,6 +7842,10 @@ static void disas_simd_indexed_vector(DisasContext *s, uint32_t insn)
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case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
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case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
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case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */
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if (is_scalar) {
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unallocated_encoding(s);
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return;
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}
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is_long = true;
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break;
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case 0x3: /* SQDMLAL, SQDMLAL2 */
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@ -7856,12 +7855,17 @@ static void disas_simd_indexed_vector(DisasContext *s, uint32_t insn)
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/* fall through */
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case 0xc: /* SQDMULH */
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case 0xd: /* SQRDMULH */
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case 0x8: /* MUL */
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if (u) {
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unallocated_encoding(s);
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return;
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}
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break;
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case 0x8: /* MUL */
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if (u || is_scalar) {
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unallocated_encoding(s);
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return;
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}
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break;
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case 0x1: /* FMLA */
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case 0x5: /* FMLS */
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if (u) {
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@ -7923,7 +7927,7 @@ static void disas_simd_indexed_vector(DisasContext *s, uint32_t insn)
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read_vec_element(s, tcg_idx, rm, index, MO_64);
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for (pass = 0; pass < 2; pass++) {
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for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
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TCGv_i64 tcg_op = tcg_temp_new_i64();
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TCGv_i64 tcg_res = tcg_temp_new_i64();
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@ -7954,15 +7958,28 @@ static void disas_simd_indexed_vector(DisasContext *s, uint32_t insn)
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tcg_temp_free_i64(tcg_res);
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}
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if (is_scalar) {
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clear_vec_high(s, rd);
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}
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tcg_temp_free_i64(tcg_idx);
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} else if (!is_long) {
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/* 32 bit floating point, or 16 or 32 bit integer */
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/* 32 bit floating point, or 16 or 32 bit integer.
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* For the 16 bit scalar case we use the usual Neon helpers and
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* rely on the fact that 0 op 0 == 0 with no side effects.
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*/
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TCGv_i32 tcg_idx = tcg_temp_new_i32();
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int pass;
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int pass, maxpasses;
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if (is_scalar) {
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maxpasses = 1;
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} else {
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maxpasses = is_q ? 4 : 2;
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}
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read_vec_element_i32(s, tcg_idx, rm, index, size);
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if (size == 1) {
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if (size == 1 && !is_scalar) {
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/* The simplest way to handle the 16x16 indexed ops is to duplicate
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* the index into both halves of the 32 bit tcg_idx and then use
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* the usual Neon helpers.
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@ -7970,11 +7987,11 @@ static void disas_simd_indexed_vector(DisasContext *s, uint32_t insn)
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tcg_gen_deposit_i32(tcg_idx, tcg_idx, tcg_idx, 16, 16);
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}
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for (pass = 0; pass < (is_q ? 4 : 2); pass++) {
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for (pass = 0; pass < maxpasses; pass++) {
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TCGv_i32 tcg_op = tcg_temp_new_i32();
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TCGv_i32 tcg_res = tcg_temp_new_i32();
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read_vec_element_i32(s, tcg_op, rn, pass, MO_32);
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read_vec_element_i32(s, tcg_op, rn, pass, is_scalar ? size : MO_32);
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switch (opcode) {
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case 0x0: /* MLA */
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@ -8038,7 +8055,12 @@ static void disas_simd_indexed_vector(DisasContext *s, uint32_t insn)
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g_assert_not_reached();
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}
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write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
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if (is_scalar) {
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write_fp_sreg(s, rd, tcg_res);
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} else {
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write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
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}
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tcg_temp_free_i32(tcg_op);
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tcg_temp_free_i32(tcg_res);
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}
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@ -8064,11 +8086,18 @@ static void disas_simd_indexed_vector(DisasContext *s, uint32_t insn)
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read_vec_element(s, tcg_idx, rm, index, memop);
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for (pass = 0; pass < 2; pass++) {
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for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
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TCGv_i64 tcg_op = tcg_temp_new_i64();
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TCGv_i64 tcg_passres;
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int passelt;
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read_vec_element(s, tcg_op, rn, pass + (is_q * 2), memop);
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if (is_scalar) {
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passelt = 0;
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} else {
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passelt = pass + (is_q * 2);
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}
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read_vec_element(s, tcg_op, rn, passelt, memop);
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tcg_res[pass] = tcg_temp_new_i64();
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@ -8116,23 +8145,35 @@ static void disas_simd_indexed_vector(DisasContext *s, uint32_t insn)
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tcg_temp_free_i64(tcg_passres);
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}
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tcg_temp_free_i64(tcg_idx);
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if (is_scalar) {
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clear_vec_high(s, rd);
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}
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} else {
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TCGv_i32 tcg_idx = tcg_temp_new_i32();
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assert(size == 1);
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read_vec_element_i32(s, tcg_idx, rm, index, size);
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/* The simplest way to handle the 16x16 indexed ops is to duplicate
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* the index into both halves of the 32 bit tcg_idx and then use
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* the usual Neon helpers.
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*/
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tcg_gen_deposit_i32(tcg_idx, tcg_idx, tcg_idx, 16, 16);
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if (!is_scalar) {
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/* The simplest way to handle the 16x16 indexed ops is to
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* duplicate the index into both halves of the 32 bit tcg_idx
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* and then use the usual Neon helpers.
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*/
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tcg_gen_deposit_i32(tcg_idx, tcg_idx, tcg_idx, 16, 16);
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}
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for (pass = 0; pass < 2; pass++) {
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for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
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TCGv_i32 tcg_op = tcg_temp_new_i32();
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TCGv_i64 tcg_passres;
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read_vec_element_i32(s, tcg_op, rn, pass + (is_q * 2), MO_32);
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if (is_scalar) {
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read_vec_element_i32(s, tcg_op, rn, pass, size);
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} else {
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read_vec_element_i32(s, tcg_op, rn,
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pass + (is_q * 2), MO_32);
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}
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tcg_res[pass] = tcg_temp_new_i64();
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if (opcode == 0xa || opcode == 0xb) {
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@ -8183,6 +8224,14 @@ static void disas_simd_indexed_vector(DisasContext *s, uint32_t insn)
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tcg_temp_free_i64(tcg_passres);
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}
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tcg_temp_free_i32(tcg_idx);
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if (is_scalar) {
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tcg_gen_ext32u_i64(tcg_res[0], tcg_res[0]);
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}
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}
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if (is_scalar) {
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tcg_res[1] = tcg_const_i64(0);
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}
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for (pass = 0; pass < 2; pass++) {
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@ -8241,7 +8290,7 @@ static const AArch64DecodeTable data_proc_simd[] = {
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{ 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc },
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{ 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes },
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{ 0x0e000400, 0x9fe08400, disas_simd_copy },
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{ 0x0f000000, 0x9f000400, disas_simd_indexed_vector },
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{ 0x0f000000, 0x9f000400, disas_simd_indexed }, /* vector indexed */
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/* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
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{ 0x0f000400, 0x9ff80400, disas_simd_mod_imm },
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{ 0x0f000400, 0x9f800400, disas_simd_shift_imm },
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@ -8253,7 +8302,7 @@ static const AArch64DecodeTable data_proc_simd[] = {
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{ 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc },
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{ 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise },
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{ 0x5e000400, 0xdfe08400, disas_simd_scalar_copy },
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{ 0x5f000000, 0xdf000400, disas_simd_scalar_indexed },
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{ 0x5f000000, 0xdf000400, disas_simd_indexed }, /* scalar indexed */
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{ 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm },
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{ 0x4e280800, 0xff3e0c00, disas_crypto_aes },
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{ 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha },
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