OpenE2K/qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

kvm/powerpc: Add irq support for E500 core

Browse Source 
Signed-off-by: Liu Yu <yu.liu@freescale.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6662 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32 2009-03-02 16:42:32 +00:00
parent 74c62ba889
commit 9fdc60bf55
4 changed files with 74 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

60
hw/ppc.c
View File

@ -314,6 +314,66 @@ void ppc40x_irq_init (CPUState *env)
env, PPC40x_INPUT_NB);
}
/* PowerPC E500 internal IRQ controller */
static void ppce500_set_irq (void *opaque, int pin, int level)
{
CPUState *env = opaque;
int cur_level;
LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
env, pin, level);
cur_level = (env->irq_input_state >> pin) & 1;
/* Don't generate spurious events */
if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
switch (pin) {
case PPCE500_INPUT_MCK:
if (level) {
LOG_IRQ("%s: reset the PowerPC system\n",
__func__);
qemu_system_reset_request();
}
break;
case PPCE500_INPUT_RESET_CORE:
if (level) {
LOG_IRQ("%s: reset the PowerPC core\n", __func__);
ppc_set_irq(env, PPC_INTERRUPT_MCK, level);
}
break;
case PPCE500_INPUT_CINT:
/* Level sensitive - active high */
LOG_IRQ("%s: set the critical IRQ state to %d\n",
__func__, level);
ppc_set_irq(env, PPC_INTERRUPT_CEXT, level);
break;
case PPCE500_INPUT_INT:
/* Level sensitive - active high */
LOG_IRQ("%s: set the core IRQ state to %d\n",
__func__, level);
ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
break;
case PPCE500_INPUT_DEBUG:
/* Level sensitive - active high */
LOG_IRQ("%s: set the debug pin state to %d\n",
__func__, level);
ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level);
break;
default:
/* Unknown pin - do nothing */
LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
return;
}
if (level)
env->irq_input_state |= 1 << pin;
else
env->irq_input_state &= ~(1 << pin);
}
}
void ppce500_irq_init (CPUState *env)
{
env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq,
env, PPCE500_INPUT_NB);
}
/*****************************************************************************/
/* PowerPC time base and decrementer emulation */
struct ppc_tb_t {

1
hw/ppc.h
View File

@ -31,6 +31,7 @@ extern CPUReadMemoryFunc *PPC_io_read[];
void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
void ppc40x_irq_init (CPUState *env);
void ppce500_irq_init (CPUState *env);
void ppc6xx_irq_init (CPUState *env);
void ppc970_irq_init (CPUState *env);

10
target-ppc/cpu.h
View File

@ -1355,6 +1355,16 @@ enum {
PPCBookE_INPUT_NB,
};
enum {
/* PowerPC E500 input pins */
PPCE500_INPUT_RESET_CORE = 0,
PPCE500_INPUT_MCK = 1,
PPCE500_INPUT_CINT = 3,
PPCE500_INPUT_INT = 4,
PPCE500_INPUT_DEBUG = 6,
PPCE500_INPUT_NB,
};
enum {
/* PowerPC 40x input pins */
PPC40x_INPUT_RESET_CORE = 0,

5
target-ppc/translate_init.c
View File

@ -63,6 +63,7 @@ void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
PPC_IRQ_INIT_FN(40x);
PPC_IRQ_INIT_FN(6xx);
PPC_IRQ_INIT_FN(970);
PPC_IRQ_INIT_FN(e500);
/* Generic callbacks:
* do nothing but store/retrieve spr value
@ -4198,7 +4199,6 @@ static void init_proc_e300 (CPUPPCState *env)
#define check_pow_e500v2 check_pow_hid0
#define init_proc_e500v2 init_proc_e500
__attribute__ (( unused ))
static void init_proc_e500 (CPUPPCState *env)
{
/* Time base */
@ -4300,7 +4300,8 @@ static void init_proc_e500 (CPUPPCState *env)
init_excp_e200(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* XXX: TODO: allocate internal IRQ controller */
/* Allocate hardware IRQ controller */
ppce500_irq_init(env);
}
/* Non-embedded PowerPC */