From a04ca92a54776d832e719252b252c69339b28ec7 Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Fri, 3 Sep 2021 12:32:21 +0100 Subject: [PATCH] escc: remove register changes from escc_reset_chn() Now that register values at reset are handled elsewhere for all of device reset, soft reset and hard reset, escc_reset_chn() only needs to handle initialisation of internal device state. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell Message-Id: <20210903113223.19551-8-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland --- hw/char/escc.c | 25 ------------------------- 1 file changed, 25 deletions(-) diff --git a/hw/char/escc.c b/hw/char/escc.c index 80f1d1b8fc..22c97414a1 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -139,7 +139,6 @@ #define MISC2_PLLCMD0 0x20 #define MISC2_PLLCMD1 0x40 #define MISC2_PLLCMD2 0x80 -#define MISC2_PLLDIS 0x30 #define W_EXTINT 15 #define EXTINT_DCD 0x08 #define EXTINT_SYNCINT 0x10 @@ -279,31 +278,7 @@ static void escc_update_irq(ESCCChannelState *s) static void escc_reset_chn(ESCCChannelState *s) { - int i; - s->reg = 0; - for (i = 0; i < ESCC_SERIAL_REGS; i++) { - s->rregs[i] = 0; - s->wregs[i] = 0; - } - /* 1X divisor, 1 stop bit, no parity */ - s->wregs[W_TXCTRL1] = TXCTRL1_1STOP; - s->wregs[W_MINTR] = MINTR_RST_ALL; - /* Synch mode tx clock = TRxC */ - s->wregs[W_CLOCK] = CLOCK_TRXC; - /* PLL disabled */ - s->wregs[W_MISC2] = MISC2_PLLDIS; - /* Enable most interrupts */ - s->wregs[W_EXTINT] = EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT | - EXTINT_TXUNDRN | EXTINT_BRKINT; - if (s->disabled) { - s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_DCD | STATUS_SYNC | - STATUS_CTS | STATUS_TXUNDRN; - } else { - s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_TXUNDRN; - } - s->rregs[R_SPEC] = SPEC_BITS8 | SPEC_ALLSENT; - s->rx = s->tx = 0; s->rxint = s->txint = 0; s->rxint_under_svc = s->txint_under_svc = 0;