From a0d805f035ff7132949a4a7e82d7742c243927ed Mon Sep 17 00:00:00 2001 From: Weiwei Li Date: Wed, 15 Feb 2023 10:05:27 +0800 Subject: [PATCH] target/riscv: Fix the relationship between Zhinxmin and Zhinx Just like zfh and zfhmin, Zhinxmin is part of Zhinx so Zhinxmin will be enabled when Zhinx is enabled. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza Message-ID: <20230215020539.4788-3-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a717f5d995..dcd85f7f27 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -754,8 +754,11 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) } /* Set the ISA extensions, checks should have happened above */ - if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || - cpu->cfg.ext_zhinxmin) { + if (cpu->cfg.ext_zhinx) { + cpu->cfg.ext_zhinxmin = true; + } + + if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) { cpu->cfg.ext_zfinx = true; }