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accel/tcg: Add tlb_fill_flags to CPUTLBEntryFull

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Allow the target to set tlb flags to apply to all of the
comparators.  Remove MemTxAttrs.byte_swap, as the bit is
not relevant to memory transactions, only the page mapping.
Adjust target/sparc to set TLB_BSWAP directly.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240301204110.656742-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2024-03-01 10:41:07 -10:00 committed by Peter Maydell
parent a1a85a9502
commit a0ff4a879c
4 changed files with 5 additions and 7 deletions
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5
accel/tcg/cputlb.c
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@ -1145,14 +1145,11 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx,
" prot=%x idx=%d\n", " prot=%x idx=%d\n",
addr, full->phys_addr, prot, mmu_idx); addr, full->phys_addr, prot, mmu_idx);
read_flags = 0; read_flags = full->tlb_fill_flags;
if (full->lg_page_size < TARGET_PAGE_BITS) { if (full->lg_page_size < TARGET_PAGE_BITS) {
/* Repeat the MMU check and TLB fill on every access. */ /* Repeat the MMU check and TLB fill on every access. */
read_flags |= TLB_INVALID_MASK; read_flags |= TLB_INVALID_MASK;
} }
if (full->attrs.byte_swap) {
read_flags |= TLB_BSWAP;
}
is_ram = memory_region_is_ram(section->mr); is_ram = memory_region_is_ram(section->mr);
is_romd = memory_region_is_romd(section->mr); is_romd = memory_region_is_romd(section->mr);

2
include/exec/memattrs.h
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@ -52,8 +52,6 @@ typedef struct MemTxAttrs {
unsigned int memory:1; unsigned int memory:1;
/* Requester ID (for MSI for example) */ /* Requester ID (for MSI for example) */
unsigned int requester_id:16; unsigned int requester_id:16;
/* Invert endianness for this page */
unsigned int byte_swap:1;
} MemTxAttrs; } MemTxAttrs;
/* Bus masters which don't specify any attributes will get this, /* Bus masters which don't specify any attributes will get this,

3
include/hw/core/cpu.h
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@ -230,6 +230,9 @@ typedef struct CPUTLBEntryFull {
/* @lg_page_size contains the log2 of the page size. */ /* @lg_page_size contains the log2 of the page size. */
uint8_t lg_page_size; uint8_t lg_page_size;
/* Additional tlb flags requested by tlb_fill. */
uint8_t tlb_fill_flags;
/* /*
* Additional tlb flags for use by the slow path. If non-zero, * Additional tlb flags for use by the slow path. If non-zero,
* the corresponding CPUTLBEntry comparator must have TLB_FORCE_SLOW. * the corresponding CPUTLBEntry comparator must have TLB_FORCE_SLOW.

2
target/sparc/mmu_helper.c
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@ -580,7 +580,7 @@ static int get_physical_address_data(CPUSPARCState *env, CPUTLBEntryFull *full,
int do_fault = 0; int do_fault = 0;
if (TTE_IS_IE(env->dtlb[i].tte)) { if (TTE_IS_IE(env->dtlb[i].tte)) {
full->attrs.byte_swap = true; full->tlb_fill_flags |= TLB_BSWAP;
} }
/* access ok? */ /* access ok? */