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target/riscv: Add rev8 instruction, removing grev/grevi 

The 1.0.0 version of Zbb does not contain grev/grevi.  Instead, a
rev8 instruction (equivalent to the rev8 pseudo-instruction built on
grevi from pre-0.93 draft-B) is available.

This commit adds the new rev8 instruction and removes grev/grevi.

Note that there is no W-form of this instruction (both a
sign-extending and zero-extending 32-bit version can easily be
synthesized by following rev8 with either a srai or srli instruction
on RV64) and that the opcode encodings for rev8 in RV32 and RV64 are
different.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210911140016.834071-14-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Philipp Tomsich 2021-09-11 16:00:13 +02:00 committed by Alistair Francis
parent 7e68e6c79b
commit a1095bdcb0
4 changed files with 15 additions and 79 deletions
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40
target/riscv/bitmanip_helper.c
View File

@ -24,46 +24,6 @@
#include "exec/helper-proto.h"
#include "tcg/tcg.h"
static const uint64_t adjacent_masks[] = {
dup_const(MO_8, 0x55),
dup_const(MO_8, 0x33),
dup_const(MO_8, 0x0f),
dup_const(MO_16, 0xff),
dup_const(MO_32, 0xffff),
UINT32_MAX
};
static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shift)
{
return ((x & mask) << shift) | ((x & ~mask) >> shift);
}
static target_ulong do_grev(target_ulong rs1,
target_ulong rs2,
int bits)
{
target_ulong x = rs1;
int i, shift;
for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) {
if (rs2 & shift) {
x = do_swap(x, adjacent_masks[i], shift);
}
}
return x;
}
target_ulong HELPER(grev)(target_ulong rs1, target_ulong rs2)
{
return do_grev(rs1, rs2, TARGET_LONG_BITS);
}
target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
{
return do_grev(rs1, rs2, 32);
}
target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
{
target_ulong result = 0;

2
target/riscv/helper.h
View File

@ -59,8 +59,6 @@ DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, tl)
DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
/* Bitmanip */
DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)

12
target/riscv/insn32.decode
View File

@ -683,6 +683,9 @@ min 0000101 .......... 100 ..... 0110011 @r
minu 0000101 .......... 101 ..... 0110011 @r
orc_b 001010 000111 ..... 101 ..... 0010011 @r2
orn 0100000 .......... 110 ..... 0110011 @r
# The encoding for rev8 differs between RV32 and RV64.
# rev8_32 denotes the RV32 variant.
rev8_32 011010 011000 ..... 101 ..... 0010011 @r2
rol 0110000 .......... 001 ..... 0110011 @r
ror 0110000 .......... 101 ..... 0110011 @r
rori 01100 ............ 101 ..... 0010011 @sh
@ -694,6 +697,10 @@ xnor 0100000 .......... 100 ..... 0110011 @r
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
# The encoding for rev8 differs between RV32 and RV64.
# When executing on RV64, the encoding used in RV32 is an illegal
# instruction, so we use different handler functions to differentiate.
rev8_64 011010 111000 ..... 101 ..... 0010011 @r2
rolw 0110000 .......... 001 ..... 0111011 @r
roriw 0110000 .......... 101 ..... 0011011 @sh5
rorw 0110000 .......... 101 ..... 0111011 @r
@ -702,15 +709,10 @@ rorw 0110000 .......... 101 ..... 0111011 @r
pack 0000100 .......... 100 ..... 0110011 @r
packu 0100100 .......... 100 ..... 0110011 @r
packh 0000100 .......... 111 ..... 0110011 @r
grev 0110100 .......... 101 ..... 0110011 @r
grevi 01101. ........... 101 ..... 0010011 @sh
# *** RV64B Standard Extension (in addition to RV32B) ***
packw 0000100 .......... 100 ..... 0111011 @r
packuw 0100100 .......... 100 ..... 0111011 @r
grevw 0110100 .......... 101 ..... 0111011 @r
greviw 0110100 .......... 101 ..... 0011011 @sh5
# *** RV32 Zbc Standard Extension ***
clmul 0000101 .......... 001 ..... 0110011 @r

40
target/riscv/insn_trans/trans_rvb.c.inc
View File

@ -273,26 +273,18 @@ static bool trans_rol(DisasContext *ctx, arg_rol *a)
return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
}
static bool trans_grev(DisasContext *ctx, arg_grev *a)
static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
{
REQUIRE_EXT(ctx, RVB);
return gen_shift(ctx, a, EXT_NONE, gen_helper_grev);
REQUIRE_32BIT(ctx);
REQUIRE_ZBB(ctx);
return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
}
static void gen_grevi(TCGv dest, TCGv src, target_long shamt)
static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
{
if (shamt == TARGET_LONG_BITS - 8) {
/* rev8, byte swaps */
tcg_gen_bswap_tl(dest, src);
} else {
gen_helper_grev(dest, src, tcg_constant_tl(shamt));
}
}
static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
{
REQUIRE_EXT(ctx, RVB);
return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_grevi);
REQUIRE_64BIT(ctx);
REQUIRE_ZBB(ctx);
return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
}
static void gen_orc_b(TCGv ret, TCGv source1)
@ -471,22 +463,6 @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
return gen_shift(ctx, a, EXT_NONE, gen_rolw);
}
static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
ctx->w = true;
return gen_shift(ctx, a, EXT_ZERO, gen_helper_grev);
}
static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
ctx->w = true;
return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_grev);
}
#define GEN_SHADD_UW(SHAMT) \
static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
{ \