PowerPC coding style and inlining fixes.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3461 c046a42c-6fe2-441c-8c8c-71466251a162
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j_mayer
parent
5bda28432f
commit
a11b8151df
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@ -232,22 +232,24 @@ static always_inline int _pte_check (mmu_ctx_t *ctx, int is_64b,
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return ret;
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}
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static int pte32_check (mmu_ctx_t *ctx, target_ulong pte0, target_ulong pte1,
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int h, int rw, int type)
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static always_inline int pte32_check (mmu_ctx_t *ctx,
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target_ulong pte0, target_ulong pte1,
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int h, int rw, int type)
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{
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return _pte_check(ctx, 0, pte0, pte1, h, rw, type);
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}
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#if defined(TARGET_PPC64)
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static int pte64_check (mmu_ctx_t *ctx, target_ulong pte0, target_ulong pte1,
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int h, int rw, int type)
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static always_inline int pte64_check (mmu_ctx_t *ctx,
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target_ulong pte0, target_ulong pte1,
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int h, int rw, int type)
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{
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return _pte_check(ctx, 1, pte0, pte1, h, rw, type);
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}
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#endif
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static int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p,
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int ret, int rw)
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static always_inline int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p,
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int ret, int rw)
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{
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int store = 0;
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@ -272,8 +274,8 @@ static int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p,
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}
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/* Software driven TLB helpers */
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static int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr,
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int way, int is_code)
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static always_inline int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr,
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int way, int is_code)
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{
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int nr;
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@ -288,7 +290,7 @@ static int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr,
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return nr;
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}
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static void ppc6xx_tlb_invalidate_all (CPUState *env)
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static always_inline void ppc6xx_tlb_invalidate_all (CPUState *env)
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{
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ppc6xx_tlb_t *tlb;
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int nr, max;
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@ -339,8 +341,9 @@ static always_inline void __ppc6xx_tlb_invalidate_virt (CPUState *env,
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#endif
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}
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static void ppc6xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
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int is_code)
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static always_inline void ppc6xx_tlb_invalidate_virt (CPUState *env,
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target_ulong eaddr,
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int is_code)
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{
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__ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
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}
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@ -368,8 +371,9 @@ void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
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env->last_way = way;
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}
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static int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
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target_ulong eaddr, int rw, int access_type)
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static always_inline int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
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target_ulong eaddr, int rw,
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int access_type)
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{
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ppc6xx_tlb_t *tlb;
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int nr, best, way;
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@ -444,8 +448,8 @@ static int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
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}
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/* Perform BAT hit & translation */
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static int get_bat (CPUState *env, mmu_ctx_t *ctx,
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target_ulong virtual, int rw, int type)
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static always_inline int get_bat (CPUState *env, mmu_ctx_t *ctx,
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target_ulong virtual, int rw, int type)
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{
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target_ulong *BATlt, *BATut, *BATu, *BATl;
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target_ulong base, BEPIl, BEPIu, bl;
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@ -635,13 +639,13 @@ static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h,
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return ret;
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}
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static int find_pte32 (mmu_ctx_t *ctx, int h, int rw, int type)
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static always_inline int find_pte32 (mmu_ctx_t *ctx, int h, int rw, int type)
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{
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return _find_pte(ctx, 0, h, rw, type);
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}
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#if defined(TARGET_PPC64)
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static int find_pte64 (mmu_ctx_t *ctx, int h, int rw, int type)
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static always_inline int find_pte64 (mmu_ctx_t *ctx, int h, int rw, int type)
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{
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return _find_pte(ctx, 1, h, rw, type);
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}
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@ -659,18 +663,19 @@ static always_inline int find_pte (CPUState *env, mmu_ctx_t *ctx,
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}
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#if defined(TARGET_PPC64)
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static inline int slb_is_valid (uint64_t slb64)
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static always_inline int slb_is_valid (uint64_t slb64)
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{
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return slb64 & 0x0000000008000000ULL ? 1 : 0;
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}
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static inline void slb_invalidate (uint64_t *slb64)
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static always_inline void slb_invalidate (uint64_t *slb64)
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{
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*slb64 &= ~0x0000000008000000ULL;
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}
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static int slb_lookup (CPUPPCState *env, target_ulong eaddr,
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target_ulong *vsid, target_ulong *page_mask, int *attr)
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static always_inline int slb_lookup (CPUPPCState *env, target_ulong eaddr,
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target_ulong *vsid,
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target_ulong *page_mask, int *attr)
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{
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target_phys_addr_t sr_base;
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target_ulong mask;
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@ -847,8 +852,8 @@ static always_inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1,
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return (sdr1 & ((target_ulong)(-1ULL) << sdr_sh)) | (hash & mask);
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}
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static int get_segment (CPUState *env, mmu_ctx_t *ctx,
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target_ulong eaddr, int rw, int type)
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static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx,
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target_ulong eaddr, int rw, int type)
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{
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target_phys_addr_t sdr, hash, mask, sdr_mask, htab_mask;
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target_ulong sr, vsid, vsid_mask, pgidx, page_mask;
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@ -1063,10 +1068,10 @@ static int get_segment (CPUState *env, mmu_ctx_t *ctx,
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}
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/* Generic TLB check function for embedded PowerPC implementations */
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static int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb,
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target_phys_addr_t *raddrp,
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target_ulong address,
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uint32_t pid, int ext, int i)
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static always_inline int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb,
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target_phys_addr_t *raddrp,
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target_ulong address,
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uint32_t pid, int ext, int i)
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{
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target_ulong mask;
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@ -1122,7 +1127,7 @@ int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)
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}
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/* Helpers specific to PowerPC 40x implementations */
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static void ppc4xx_tlb_invalidate_all (CPUState *env)
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static always_inline void ppc4xx_tlb_invalidate_all (CPUState *env)
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{
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ppcemb_tlb_t *tlb;
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int i;
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@ -1134,8 +1139,9 @@ static void ppc4xx_tlb_invalidate_all (CPUState *env)
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tlb_flush(env, 1);
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}
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static void ppc4xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
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uint32_t pid)
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static always_inline void ppc4xx_tlb_invalidate_virt (CPUState *env,
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target_ulong eaddr,
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uint32_t pid)
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{
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#if !defined(FLUSH_ALL_TLBS)
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ppcemb_tlb_t *tlb;
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@ -1286,8 +1292,8 @@ int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
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return ret;
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}
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static int check_physical (CPUState *env, mmu_ctx_t *ctx,
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target_ulong eaddr, int rw)
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static always_inline int check_physical (CPUState *env, mmu_ctx_t *ctx,
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target_ulong eaddr, int rw)
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{
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int in_plb, ret;
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@ -1986,7 +1992,7 @@ void ppc_hw_interrupt (CPUState *env)
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env->error_code = 0;
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}
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#else /* defined (CONFIG_USER_ONLY) */
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static void dump_syscall (CPUState *env)
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static always_inline void dump_syscall (CPUState *env)
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{
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fprintf(logfile, "syscall r0=0x" REGX " r3=0x" REGX " r4=0x" REGX
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" r5=0x" REGX " r6=0x" REGX " nip=0x" ADDRX "\n",
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@ -474,7 +474,7 @@ void do_popcntb_64 (void)
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/*****************************************************************************/
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/* Floating point operations helpers */
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static inline int fpisneg (float64 f)
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static always_inline int fpisneg (float64 f)
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{
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union {
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float64 f;
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@ -486,7 +486,7 @@ static inline int fpisneg (float64 f)
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return u.u >> 63 != 0;
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}
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static inline int isden (float f)
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static always_inline int isden (float f)
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{
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union {
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float64 f;
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@ -498,7 +498,7 @@ static inline int isden (float f)
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return ((u.u >> 52) & 0x7FF) == 0;
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}
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static inline int iszero (float64 f)
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static always_inline int iszero (float64 f)
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{
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union {
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float64 f;
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@ -510,7 +510,7 @@ static inline int iszero (float64 f)
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return (u.u & ~0x8000000000000000ULL) == 0;
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}
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static inline int isinfinity (float64 f)
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static always_inline int isinfinity (float64 f)
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{
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union {
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float64 f;
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@ -661,7 +661,6 @@ static always_inline void float_zero_divide_excp (void)
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float64 f;
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uint64_t u;
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} u0, u1;
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env->fpscr |= 1 << FPSCR_ZX;
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env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
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@ -2825,12 +2824,12 @@ void do_load_74xx_tlb (int is_code)
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way, is_code, CMP, RPN);
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}
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static target_ulong booke_tlb_to_page_size (int size)
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static always_inline target_ulong booke_tlb_to_page_size (int size)
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{
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return 1024 << (2 * size);
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}
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static int booke_page_size_to_tlb (target_ulong page_size)
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static always_inline int booke_page_size_to_tlb (target_ulong page_size)
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{
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int size;
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@ -295,7 +295,6 @@ static void gen_##name (DisasContext *ctx); \
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GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
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static void gen_##name (DisasContext *ctx)
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typedef struct opcode_t {
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unsigned char opc1, opc2, opc3;
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#if HOST_LONG_BITS == 64 /* Explicitely align to 64 bits */
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@ -3503,7 +3502,7 @@ GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
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#endif
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}
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#if 0
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#if 1
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#define SPR_NOACCESS ((void *)(-1))
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#else
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static void spr_noaccess (void *opaque, int sprn)
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