x3130/upstream: support aer
add aer support. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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61620c2fff
commit
a158f92fa7
@ -41,7 +41,7 @@ static void xio3130_upstream_write_config(PCIDevice *d, uint32_t address,
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pci_bridge_write_config(d, address, val, len);
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pcie_cap_flr_write_config(d, address, val, len);
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msi_write_config(d, address, val, len);
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/* TODO: AER */
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pcie_aer_write_config(d, address, val, len);
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}
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static void xio3130_upstream_reset(DeviceState *qdev)
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@ -57,6 +57,7 @@ static int xio3130_upstream_initfn(PCIDevice *d)
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PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
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PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
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int rc;
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int tmp;
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rc = pci_bridge_initfn(d);
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if (rc < 0) {
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@ -72,33 +73,45 @@ static int xio3130_upstream_initfn(PCIDevice *d)
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XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
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XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT);
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if (rc < 0) {
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return rc;
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goto err_bridge;
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}
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rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET,
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XIO3130_SSVID_SVID, XIO3130_SSVID_SSID);
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if (rc < 0) {
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return rc;
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goto err_bridge;
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}
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rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM,
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p->port);
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if (rc < 0) {
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return rc;
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goto err_msi;
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}
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/* TODO: implement FLR */
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pcie_cap_flr_init(d);
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pcie_cap_deverr_init(d);
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/* TODO: AER */
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rc = pcie_aer_init(d, XIO3130_AER_OFFSET);
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if (rc < 0) {
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goto err;
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}
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return 0;
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err:
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pcie_cap_exit(d);
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err_msi:
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msi_uninit(d);
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err_bridge:
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tmp = pci_bridge_exitfn(d);
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assert(!tmp);
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return rc;
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}
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static int xio3130_upstream_exitfn(PCIDevice *d)
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{
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/* TODO: AER */
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msi_uninit(d);
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pcie_aer_exit(d);
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pcie_cap_exit(d);
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msi_uninit(d);
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return pci_bridge_exitfn(d);
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}
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@ -131,7 +144,8 @@ static const VMStateDescription vmstate_xio3130_upstream = {
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_PCIE_DEVICE(br.dev, PCIEPort),
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/* TODO: AER */
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VMSTATE_STRUCT(br.dev.exp.aer_log, PCIEPort, 0, vmstate_pcie_aer_log,
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PCIEAERLog),
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VMSTATE_END_OF_LIST()
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}
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};
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@ -151,7 +165,8 @@ static PCIDeviceInfo xio3130_upstream_info = {
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.qdev.props = (Property[]) {
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DEFINE_PROP_UINT8("port", PCIEPort, port, 0),
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/* TODO: AER */
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DEFINE_PROP_UINT16("aer_log_max", PCIEPort, br.dev.exp.aer_log.log_max,
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PCIE_AER_LOG_MAX_DEFAULT),
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DEFINE_PROP_END_OF_LIST(),
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}
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};
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