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Sixth RISC-V PR for QEMU 7.1

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This is a PR to go in for RC1. It fixes a segfault that occurs
 when using multiple sockets on the RISC-V virt board. It also
 includes a small fix to allow both Zmmul and M extensions.
 
 * Allow both Zmmul and M extension
 * Fix multi-socket plic configuraiton
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Merge tag 'pull-riscv-to-apply-20220728' of github.com:alistair23/qemu into staging

Sixth RISC-V PR for QEMU 7.1

This is a PR to go in for RC1. It fixes a segfault that occurs
when using multiple sockets on the RISC-V virt board. It also
includes a small fix to allow both Zmmul and M extensions.

* Allow both Zmmul and M extension
* Fix multi-socket plic configuraiton

# -----BEGIN PGP SIGNATURE-----
#
# iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmLh33AACgkQIeENKd+X
# cFROBQf/QFxHsIX9clpAkHmK220efQ3rjHZtdCqQoCeRZp2EytFS9KZ6iae/BM9r
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# =ip1R
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 27 Jul 2022 05:59:28 PM PDT
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* tag 'pull-riscv-to-apply-20220728' of github.com:alistair23/qemu:
  hw/intc: sifive_plic: Fix multi-socket plic configuraiton
  RISC-V: Allow both Zmmul and M

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-07-28 04:40:26 -07:00
commit a17001c423
2 changed files with 2 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
hw/intc/sifive_plic.c
View File

@ -454,10 +454,10 @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
for (i = 0; i < plic->num_addrs; i++) {
int cpu_num = plic->addr_config[i].hartid;
CPUState *cpu = qemu_get_cpu(hartid_base + cpu_num);
CPUState *cpu = qemu_get_cpu(cpu_num);
if (plic->addr_config[i].mode == PLICMode_M) {
qdev_connect_gpio_out(dev, num_harts + cpu_num,
qdev_connect_gpio_out(dev, num_harts - plic->hartid_base + cpu_num,
qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
}
if (plic->addr_config[i].mode == PLICMode_S) {

5
target/riscv/cpu.c
View File

@ -619,11 +619,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
cpu->cfg.ext_ifencei = true;
}
if (cpu->cfg.ext_m && cpu->cfg.ext_zmmul) {
warn_report("Zmmul will override M");
cpu->cfg.ext_m = false;
}
if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
error_setg(errp,
"I and E extensions are incompatible");