From a1ad913da0cb85239309cae93b7a1bf83ad3e1e5 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Mon, 27 Feb 2023 11:33:20 -1000 Subject: [PATCH] target/arm: Simplify register counting in arm_gen_dynamic_svereg_xml MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rather than increment base_reg and num, compute num from the change to base_reg at the end. Clean up some nearby comments. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Message-id: 20230227213329.793795-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/gdbstub64.c | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 811833d8de..070ba20d99 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -277,32 +277,35 @@ static void output_vector_union_type(GString *s, int reg_width) g_string_append(s, ""); } -int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) +int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg) { ARMCPU *cpu = ARM_CPU(cs); GString *s = g_string_new(NULL); DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; - int i, reg_width = (cpu->sve_max_vq * 128); - info->num = 0; + int reg_width = cpu->sve_max_vq * 128; + int base_reg = orig_base_reg; + int i; + g_string_printf(s, ""); g_string_append_printf(s, ""); g_string_append_printf(s, ""); + /* Create the vector union type. */ output_vector_union_type(s, reg_width); - /* Finally the sve prefix type */ + /* Create the predicate vector type. */ g_string_append_printf(s, "", reg_width / 8); - /* Then define each register in parts for each vq */ + /* Define the vector registers. */ for (i = 0; i < 32; i++) { g_string_append_printf(s, "", i, reg_width, base_reg++); - info->num++; } + /* fpscr & status registers */ g_string_append_printf(s, "", base_reg++); - info->num += 2; + /* Define the predicate registers. */ for (i = 0; i < 16; i++) { g_string_append_printf(s, "", i, cpu->sve_max_vq * 16, base_reg++); - info->num++; } g_string_append_printf(s, "", cpu->sve_max_vq * 16, base_reg++); + + /* Define the vector length pseudo-register. */ g_string_append_printf(s, "", base_reg++); - info->num += 2; - g_string_append_printf(s, ""); - info->desc = g_string_free(s, false); + g_string_append_printf(s, ""); + + info->desc = g_string_free(s, false); + info->num = base_reg - orig_base_reg; return info->num; }