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microblaze: Add internal base vectors reg

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Configurable at CPU synthesis/instantiation.

Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
This commit is contained in:
Edgar E. Iglesias 2013-04-23 14:27:09 +02:00
parent e3351000cd
commit a1bff71c56
3 changed files with 13 additions and 4 deletions
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1
target-microblaze/cpu-qom.h
View File

@ -56,6 +56,7 @@ typedef struct MicroBlazeCPUClass {
typedef struct MicroBlazeCPU {
/*< private >*/
CPUState parent_obj;
uint32_t base_vectors;
/*< public >*/
CPUMBState env;

8
target-microblaze/cpu.c
View File

@ -22,6 +22,7 @@
#include "cpu.h"
#include "qemu-common.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
@ -119,6 +120,11 @@ static const VMStateDescription vmstate_mb_cpu = {
.unmigratable = 1,
};
static Property mb_properties[] = {
DEFINE_PROP_UINT32("xlnx.base-vectors", MicroBlazeCPU, base_vectors, 0),
DEFINE_PROP_END_OF_LIST(),
};
static void mb_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@ -133,6 +139,8 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = mb_cpu_do_interrupt;
dc->vmsd = &vmstate_mb_cpu;
dc->props = mb_properties;
}
static const TypeInfo mb_cpu_type_info = {

8
target-microblaze/helper.c
View File

@ -152,7 +152,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
env->sregs[SR_ESR], env->iflags);
log_cpu_state_mask(CPU_LOG_INT, env, 0);
env->iflags &= ~(IMM_FLAG | D_FLAG);
env->sregs[SR_PC] = 0x20;
env->sregs[SR_PC] = cpu->base_vectors + 0x20;
break;
case EXCP_MMU:
@ -192,7 +192,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags);
log_cpu_state_mask(CPU_LOG_INT, env, 0);
env->iflags &= ~(IMM_FLAG | D_FLAG);
env->sregs[SR_PC] = 0x20;
env->sregs[SR_PC] = cpu->base_vectors + 0x20;
break;
case EXCP_IRQ:
@ -233,7 +233,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
env->sregs[SR_MSR] |= t;
env->regs[14] = env->sregs[SR_PC];
env->sregs[SR_PC] = 0x10;
env->sregs[SR_PC] = cpu->base_vectors + 0x10;
//log_cpu_state_mask(CPU_LOG_INT, env, 0);
break;
@ -252,7 +252,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
if (env->exception_index == EXCP_HW_BREAK) {
env->regs[16] = env->sregs[SR_PC];
env->sregs[SR_MSR] |= MSR_BIP;
env->sregs[SR_PC] = 0x18;
env->sregs[SR_PC] = cpu->base_vectors + 0x18;
} else
env->sregs[SR_PC] = env->btarget;
break;