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target/mips: Clean up handling of CP0 register 5

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Clean up handling of CP0 register 5.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-7-git-send-email-aleksandar.markovic@rt-rk.com>
This commit is contained in:
Aleksandar Markovic 2019-08-28 18:26:30 +02:00
parent 020fe37909
commit a1e76353e3
2 changed files with 38 additions and 32 deletions
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6
target/mips/cpu.h
View File

@ -313,6 +313,12 @@ typedef struct mips_def_t mips_def_t;
/* CP0 Register 05 */ /* CP0 Register 05 */
#define CP0_REG05__PAGEMASK 0 #define CP0_REG05__PAGEMASK 0
#define CP0_REG05__PAGEGRAIN 1 #define CP0_REG05__PAGEGRAIN 1
#define CP0_REG05__SEGCTL0 2
#define CP0_REG05__SEGCTL1 3
#define CP0_REG05__SEGCTL2 4
#define CP0_REG05__PWBASE 5
#define CP0_REG05__PWFIELD 6
#define CP0_REG05__PWSIZE 7
/* CP0 Register 06 */ /* CP0 Register 06 */
#define CP0_REG06__WIRED 0 #define CP0_REG06__WIRED 0
/* CP0 Register 07 */ /* CP0 Register 07 */

64
target/mips/translate.c
View File

@ -6998,44 +6998,44 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break; break;
case CP0_REGISTER_05: case CP0_REGISTER_05:
switch (sel) { switch (sel) {
case 0: case CP0_REG05__PAGEMASK:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
register_name = "PageMask"; register_name = "PageMask";
break; break;
case 1: case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
register_name = "PageGrain"; register_name = "PageGrain";
break; break;
case 2: case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc); CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0)); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0));
tcg_gen_ext32s_tl(arg, arg); tcg_gen_ext32s_tl(arg, arg);
register_name = "SegCtl0"; register_name = "SegCtl0";
break; break;
case 3: case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc); CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1)); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1));
tcg_gen_ext32s_tl(arg, arg); tcg_gen_ext32s_tl(arg, arg);
register_name = "SegCtl1"; register_name = "SegCtl1";
break; break;
case 4: case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc); CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2)); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2));
tcg_gen_ext32s_tl(arg, arg); tcg_gen_ext32s_tl(arg, arg);
register_name = "SegCtl2"; register_name = "SegCtl2";
break; break;
case 5: case CP0_REG05__PWBASE:
check_pw(ctx); check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWBase)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWBase));
register_name = "PWBase"; register_name = "PWBase";
break; break;
case 6: case CP0_REG05__PWFIELD:
check_pw(ctx); check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWField)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWField));
register_name = "PWField"; register_name = "PWField";
break; break;
case 7: case CP0_REG05__PWSIZE:
check_pw(ctx); check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWSize)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWSize));
register_name = "PWSize"; register_name = "PWSize";
@ -7732,42 +7732,42 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break; break;
case CP0_REGISTER_05: case CP0_REGISTER_05:
switch (sel) { switch (sel) {
case 0: case CP0_REG05__PAGEMASK:
gen_helper_mtc0_pagemask(cpu_env, arg); gen_helper_mtc0_pagemask(cpu_env, arg);
register_name = "PageMask"; register_name = "PageMask";
break; break;
case 1: case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_pagegrain(cpu_env, arg); gen_helper_mtc0_pagegrain(cpu_env, arg);
register_name = "PageGrain"; register_name = "PageGrain";
ctx->base.is_jmp = DISAS_STOP; ctx->base.is_jmp = DISAS_STOP;
break; break;
case 2: case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc); CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl0(cpu_env, arg); gen_helper_mtc0_segctl0(cpu_env, arg);
register_name = "SegCtl0"; register_name = "SegCtl0";
break; break;
case 3: case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc); CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl1(cpu_env, arg); gen_helper_mtc0_segctl1(cpu_env, arg);
register_name = "SegCtl1"; register_name = "SegCtl1";
break; break;
case 4: case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc); CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl2(cpu_env, arg); gen_helper_mtc0_segctl2(cpu_env, arg);
register_name = "SegCtl2"; register_name = "SegCtl2";
break; break;
case 5: case CP0_REG05__PWBASE:
check_pw(ctx); check_pw(ctx);
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_PWBase)); gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_PWBase));
register_name = "PWBase"; register_name = "PWBase";
break; break;
case 6: case CP0_REG05__PWFIELD:
check_pw(ctx); check_pw(ctx);
gen_helper_mtc0_pwfield(cpu_env, arg); gen_helper_mtc0_pwfield(cpu_env, arg);
register_name = "PWField"; register_name = "PWField";
break; break;
case 7: case CP0_REG05__PWSIZE:
check_pw(ctx); check_pw(ctx);
gen_helper_mtc0_pwsize(cpu_env, arg); gen_helper_mtc0_pwsize(cpu_env, arg);
register_name = "PWSize"; register_name = "PWSize";
@ -8478,41 +8478,41 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break; break;
case CP0_REGISTER_05: case CP0_REGISTER_05:
switch (sel) { switch (sel) {
case 0: case CP0_REG05__PAGEMASK:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
register_name = "PageMask"; register_name = "PageMask";
break; break;
case 1: case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
register_name = "PageGrain"; register_name = "PageGrain";
break; break;
case 2: case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc); CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0)); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0));
register_name = "SegCtl0"; register_name = "SegCtl0";
break; break;
case 3: case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc); CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1)); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1));
register_name = "SegCtl1"; register_name = "SegCtl1";
break; break;
case 4: case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc); CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2)); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2));
register_name = "SegCtl2"; register_name = "SegCtl2";
break; break;
case 5: case CP0_REG05__PWBASE:
check_pw(ctx); check_pw(ctx);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase)); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase));
register_name = "PWBase"; register_name = "PWBase";
break; break;
case 6: case CP0_REG05__PWFIELD:
check_pw(ctx); check_pw(ctx);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWField)); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWField));
register_name = "PWField"; register_name = "PWField";
break; break;
case 7: case CP0_REG05__PWSIZE:
check_pw(ctx); check_pw(ctx);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWSize)); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWSize));
register_name = "PWSize"; register_name = "PWSize";
@ -9192,41 +9192,41 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break; break;
case CP0_REGISTER_05: case CP0_REGISTER_05:
switch (sel) { switch (sel) {
case 0: case CP0_REG05__PAGEMASK:
gen_helper_mtc0_pagemask(cpu_env, arg); gen_helper_mtc0_pagemask(cpu_env, arg);
register_name = "PageMask"; register_name = "PageMask";
break; break;
case 1: case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_pagegrain(cpu_env, arg); gen_helper_mtc0_pagegrain(cpu_env, arg);
register_name = "PageGrain"; register_name = "PageGrain";
break; break;
case 2: case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc); CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl0(cpu_env, arg); gen_helper_mtc0_segctl0(cpu_env, arg);
register_name = "SegCtl0"; register_name = "SegCtl0";
break; break;
case 3: case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc); CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl1(cpu_env, arg); gen_helper_mtc0_segctl1(cpu_env, arg);
register_name = "SegCtl1"; register_name = "SegCtl1";
break; break;
case 4: case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc); CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl2(cpu_env, arg); gen_helper_mtc0_segctl2(cpu_env, arg);
register_name = "SegCtl2"; register_name = "SegCtl2";
break; break;
case 5: case CP0_REG05__PWBASE:
check_pw(ctx); check_pw(ctx);
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase)); tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase));
register_name = "PWBase"; register_name = "PWBase";
break; break;
case 6: case CP0_REG05__PWFIELD:
check_pw(ctx); check_pw(ctx);
gen_helper_mtc0_pwfield(cpu_env, arg); gen_helper_mtc0_pwfield(cpu_env, arg);
register_name = "PWField"; register_name = "PWField";
break; break;
case 7: case CP0_REG05__PWSIZE:
check_pw(ctx); check_pw(ctx);
gen_helper_mtc0_pwsize(cpu_env, arg); gen_helper_mtc0_pwsize(cpu_env, arg);
register_name = "PWSize"; register_name = "PWSize";