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target/tricore: Fix OPC2_32_RRPW_EXTR for width=0 

if width was 0 we would run into the assertion:

qemu-system-tricore: tcg/tcg-op.c:217: tcg_gen_sari_i32: Assertion `arg2 >= 0 && arg2 < 32' failed.o

The instruction manual specifies undefined behaviour for this case. So
we bring this in line with the golden Infineon simlator 'tsim', which
simply writes 0 to the result in case of width=0.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
This commit is contained in:
Bastian Koppelmann 2021-03-05 14:06:38 +01:00
parent 007479842b
commit a21993c7f9
1 changed files with 5 additions and 0 deletions
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5
target/tricore/translate.c
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@ -7000,6 +7000,11 @@ static void decode_rrpw_extract_insert(DisasContext *ctx)
switch (op2) {
case OPC2_32_RRPW_EXTR:
if (width == 0) {
tcg_gen_movi_tl(cpu_gpr_d[r3], 0);
break;
}
if (pos + width <= 32) {
/* optimize special cases */
if ((pos == 0) && (width == 8)) {