target/tricore: Fix OPC2_32_RRPW_EXTR for width=0
if width was 0 we would run into the assertion: qemu-system-tricore: tcg/tcg-op.c:217: tcg_gen_sari_i32: Assertion `arg2 >= 0 && arg2 < 32' failed.o The instruction manual specifies undefined behaviour for this case. So we bring this in line with the golden Infineon simlator 'tsim', which simply writes 0 to the result in case of width=0. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
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@ -7000,6 +7000,11 @@ static void decode_rrpw_extract_insert(DisasContext *ctx)
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switch (op2) {
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switch (op2) {
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case OPC2_32_RRPW_EXTR:
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case OPC2_32_RRPW_EXTR:
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if (width == 0) {
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tcg_gen_movi_tl(cpu_gpr_d[r3], 0);
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break;
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}
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if (pos + width <= 32) {
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if (pos + width <= 32) {
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/* optimize special cases */
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/* optimize special cases */
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if ((pos == 0) && (width == 8)) {
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if ((pos == 0) && (width == 8)) {
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