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target-microblaze: mmu: Add R_TBLX_MISS macros 

Add a R_TBLX_MISS MASK and SHIFT macros.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
This commit is contained in:
Edgar E. Iglesias 2018-04-15 23:18:49 +02:00
parent a1b48e3a3a
commit a2207b593b
2 changed files with 7 additions and 2 deletions
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5
target/microblaze/mmu.c
View File

@ -292,8 +292,9 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
v & TLB_EPN_MASK, 0, cpu_mmu_index(env, false));
if (hit) {
env->mmu.regs[MMU_R_TLBX] = lu.idx;
} else
env->mmu.regs[MMU_R_TLBX] |= 0x80000000;
} else {
env->mmu.regs[MMU_R_TLBX] |= R_TBLX_MISS_MASK;
}
break;
}
default:

4
target/microblaze/mmu.h
View File

@ -54,6 +54,10 @@
#define TLB_M 0x00000002 /* Memory is coherent */
#define TLB_G 0x00000001 /* Memory is guarded from prefetch */
/* TLBX */
#define R_TBLX_MISS_SHIFT 31
#define R_TBLX_MISS_MASK (1U << R_TBLX_MISS_SHIFT)
#define TLB_ENTRIES 64
struct microblaze_mmu