target-microblaze: mmu: Add R_TBLX_MISS macros
Add a R_TBLX_MISS MASK and SHIFT macros. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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@ -292,8 +292,9 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
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v & TLB_EPN_MASK, 0, cpu_mmu_index(env, false));
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if (hit) {
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env->mmu.regs[MMU_R_TLBX] = lu.idx;
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} else
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env->mmu.regs[MMU_R_TLBX] |= 0x80000000;
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} else {
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env->mmu.regs[MMU_R_TLBX] |= R_TBLX_MISS_MASK;
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}
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break;
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}
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default:
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@ -54,6 +54,10 @@
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#define TLB_M 0x00000002 /* Memory is coherent */
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#define TLB_G 0x00000001 /* Memory is guarded from prefetch */
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/* TLBX */
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#define R_TBLX_MISS_SHIFT 31
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#define R_TBLX_MISS_MASK (1U << R_TBLX_MISS_SHIFT)
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#define TLB_ENTRIES 64
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struct microblaze_mmu
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