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target/hexagon: translation changes 

Change cpu_ldl_code to translator_ldl.
Don't end the TB after every packet when HEX_DEBUG is on.
Make gen_check_store_width a simple call.

Reported-by: Richard Henderson <<richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id: <1615783984-25918-1-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Taylor Simpson 2021-03-14 23:53:04 -05:00 committed by Richard Henderson
parent 8f860d2633
commit a27c100c23
1 changed files with 9 additions and 17 deletions
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26
target/hexagon/translate.c
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@ -88,8 +88,8 @@ static int read_packet_words(CPUHexagonState *env, DisasContext *ctx,
memset(words, 0, PACKET_WORDS_MAX * sizeof(uint32_t));
for (nwords = 0; !found_end && nwords < PACKET_WORDS_MAX; nwords++) {
words[nwords] = cpu_ldl_code(env,
ctx->base.pc_next + nwords * sizeof(uint32_t));
words[nwords] =
translator_ldl(env, ctx->base.pc_next + nwords * sizeof(uint32_t));
found_end = is_packet_end(words[nwords]);
}
if (!found_end) {
@ -292,20 +292,16 @@ static void gen_pred_writes(DisasContext *ctx, Packet *pkt)
tcg_temp_free(pval);
}
#if HEX_DEBUG
static inline void gen_check_store_width(DisasContext *ctx, int slot_num)
static void gen_check_store_width(DisasContext *ctx, int slot_num)
{
#if HEX_DEBUG
TCGv slot = tcg_const_tl(slot_num);
TCGv check = tcg_const_tl(ctx->store_width[slot_num]);
gen_helper_debug_check_store_width(cpu_env, slot, check);
tcg_temp_free(slot);
tcg_temp_free(check);
}
#define HEX_DEBUG_GEN_CHECK_STORE_WIDTH(ctx, slot_num) \
gen_check_store_width(ctx, slot_num)
#else
#define HEX_DEBUG_GEN_CHECK_STORE_WIDTH(ctx, slot_num) /* nothing */
#endif
}
static bool slot_is_predicated(Packet *pkt, int slot_num)
{
@ -355,25 +351,25 @@ void process_store(DisasContext *ctx, Packet *pkt, int slot_num)
*/
switch (ctx->store_width[slot_num]) {
case 1:
HEX_DEBUG_GEN_CHECK_STORE_WIDTH(ctx, slot_num);
gen_check_store_width(ctx, slot_num);
tcg_gen_qemu_st8(hex_store_val32[slot_num],
hex_store_addr[slot_num],
ctx->mem_idx);
break;
case 2:
HEX_DEBUG_GEN_CHECK_STORE_WIDTH(ctx, slot_num);
gen_check_store_width(ctx, slot_num);
tcg_gen_qemu_st16(hex_store_val32[slot_num],
hex_store_addr[slot_num],
ctx->mem_idx);
break;
case 4:
HEX_DEBUG_GEN_CHECK_STORE_WIDTH(ctx, slot_num);
gen_check_store_width(ctx, slot_num);
tcg_gen_qemu_st32(hex_store_val32[slot_num],
hex_store_addr[slot_num],
ctx->mem_idx);
break;
case 8:
HEX_DEBUG_GEN_CHECK_STORE_WIDTH(ctx, slot_num);
gen_check_store_width(ctx, slot_num);
tcg_gen_qemu_st64(hex_store_val64[slot_num],
hex_store_addr[slot_num],
ctx->mem_idx);
@ -593,10 +589,6 @@ static void hexagon_tr_translate_packet(DisasContextBase *dcbase, CPUState *cpu)
if (hex_cpu->lldb_compat && qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
ctx->base.is_jmp = DISAS_TOO_MANY;
}
#if HEX_DEBUG
/* When debugging, only put one packet per TB */
ctx->base.is_jmp = DISAS_TOO_MANY;
#endif
}
}