From 7386ae6372cc07c77a39cb3aa185848b43f7ae34 Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Tue, 7 Jun 2016 17:39:36 +0200 Subject: [PATCH 1/8] ppc/spapr: Refactor h_client_architecture_support() CPU parsing code The h_client_architecture_support() function has become quite big and nested already. So factor out the code that takes care of the sPAPR compatibility PVRs (which will be modified by the following patches). Signed-off-by: Thomas Huth Reviewed-by: Michael Roth Signed-off-by: David Gibson --- hw/ppc/spapr_hcall.c | 61 ++++++++++++++++++++++++++------------------ 1 file changed, 36 insertions(+), 25 deletions(-) diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 9a3f4ecc1e..bb8f4de1d7 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -922,6 +922,39 @@ static void do_set_compat(void *arg) ((cpuver) == CPU_POWERPC_LOGICAL_2_06_PLUS) ? 2061 : \ ((cpuver) == CPU_POWERPC_LOGICAL_2_07) ? 2070 : 0) +static void cas_handle_compat_cpu(PowerPCCPUClass *pcc, uint32_t pvr, + unsigned max_lvl, unsigned *compat_lvl, + unsigned *cpu_version) +{ + unsigned lvl = get_compat_level(pvr); + bool is205, is206; + + if (!lvl) { + return; + } + + /* If it is a logical PVR, try to determine the highest level */ + is205 = (pcc->pcr_mask & PCR_COMPAT_2_05) && + (lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_05)); + is206 = (pcc->pcr_mask & PCR_COMPAT_2_06) && + ((lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_06)) || + (lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_06_PLUS))); + + if (is205 || is206) { + if (!max_lvl) { + /* User did not set the level, choose the highest */ + if (*compat_lvl <= lvl) { + *compat_lvl = lvl; + *cpu_version = pvr; + } + } else if (max_lvl >= lvl) { + /* User chose the level, don't set higher than this */ + *compat_lvl = lvl; + *cpu_version = pvr; + } + } +} + #define OV5_DRCONF_MEMORY 0x20 static target_ulong h_client_architecture_support(PowerPCCPU *cpu_, @@ -931,7 +964,7 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu_, { target_ulong list = ppc64_phys_to_real(args[0]); target_ulong ov_table, ov5; - PowerPCCPUClass *pcc_ = POWERPC_CPU_GET_CLASS(cpu_); + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu_); CPUState *cs; bool cpu_match = false, cpu_update = true, memory_update = false; unsigned old_cpu_version = cpu_->cpu_version; @@ -958,29 +991,7 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu_, cpu_match = true; cpu_version = cpu_->cpu_version; } else if (!cpu_match) { - /* If it is a logical PVR, try to determine the highest level */ - unsigned lvl = get_compat_level(pvr); - if (lvl) { - bool is205 = (pcc_->pcr_mask & PCR_COMPAT_2_05) && - (lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_05)); - bool is206 = (pcc_->pcr_mask & PCR_COMPAT_2_06) && - ((lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_06)) || - (lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_06_PLUS))); - - if (is205 || is206) { - if (!max_lvl) { - /* User did not set the level, choose the highest */ - if (compat_lvl <= lvl) { - compat_lvl = lvl; - cpu_version = pvr; - } - } else if (max_lvl >= lvl) { - /* User chose the level, don't set higher than this */ - compat_lvl = lvl; - cpu_version = pvr; - } - } - } + cas_handle_compat_cpu(pcc, pvr, max_lvl, &compat_lvl, &cpu_version); } /* Terminator record */ if (~pvr_mask & pvr) { @@ -990,7 +1001,7 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu_, /* Parsing finished */ trace_spapr_cas_pvr(cpu_->cpu_version, cpu_match, - cpu_version, pcc_->pcr_mask); + cpu_version, pcc->pcr_mask); /* Update CPUs */ if (old_cpu_version != cpu_version) { From 8cd2ce7aaa3c3fadc561f40045d4d53ff72e94ef Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Tue, 7 Jun 2016 17:39:37 +0200 Subject: [PATCH 2/8] ppc: Split pcr_mask settings into supported bits and the register mask The current pcr_mask values are ambiguous: Should these be the mask that defines valid bits in the PCR register? Or should these rather indicate which compatibility levels are possible? Anyway, POWER6 and POWER7 should certainly not use the same values here. So let's introduce an additional variable "pcr_supported" here which is used to indicate the valid compatibility levels, and use pcr_mask to signal the valid bits in the PCR register. Signed-off-by: Thomas Huth Signed-off-by: David Gibson --- hw/ppc/spapr_hcall.c | 4 ++-- target-ppc/cpu-qom.h | 3 ++- target-ppc/cpu.h | 1 + target-ppc/translate_init.c | 6 ++++-- 4 files changed, 9 insertions(+), 5 deletions(-) diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index bb8f4de1d7..cc16249a8c 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -934,9 +934,9 @@ static void cas_handle_compat_cpu(PowerPCCPUClass *pcc, uint32_t pvr, } /* If it is a logical PVR, try to determine the highest level */ - is205 = (pcc->pcr_mask & PCR_COMPAT_2_05) && + is205 = (pcc->pcr_supported & PCR_COMPAT_2_05) && (lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_05)); - is206 = (pcc->pcr_mask & PCR_COMPAT_2_06) && + is206 = (pcc->pcr_supported & PCR_COMPAT_2_06) && ((lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_06)) || (lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_06_PLUS))); diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h index 07358aadf3..969ecdfbd4 100644 --- a/target-ppc/cpu-qom.h +++ b/target-ppc/cpu-qom.h @@ -165,7 +165,8 @@ typedef struct PowerPCCPUClass { uint32_t pvr; bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr); - uint64_t pcr_mask; + uint64_t pcr_mask; /* Available bits in PCR register */ + uint64_t pcr_supported; /* Bits for supported PowerISA versions */ uint32_t svr; uint64_t insns_flags; uint64_t insns_flags2; diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index cb8b9122f3..9087a08002 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -2200,6 +2200,7 @@ enum { enum { PCR_COMPAT_2_05 = 1ull << (63-62), PCR_COMPAT_2_06 = 1ull << (63-61), + PCR_COMPAT_2_07 = 1ull << (63-60), PCR_VEC_DIS = 1ull << (63-0), /* Vec. disable (bit NA since POWER8) */ PCR_VSX_DIS = 1ull << (63-1), /* VSX disable (bit NA since POWER8) */ PCR_TM_DIS = 1ull << (63-2), /* Trans. memory disable (POWER8) */ diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index a1db5009c4..fa09183f2f 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -8365,7 +8365,8 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) dc->desc = "POWER7"; dc->props = powerpc_servercpu_properties; pcc->pvr_match = ppc_pvr_match_power7; - pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06; + pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; + pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; pcc->init_proc = init_proc_POWER7; pcc->check_pow = check_pow_nocheck; pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | @@ -8445,7 +8446,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) dc->desc = "POWER8"; dc->props = powerpc_servercpu_properties; pcc->pvr_match = ppc_pvr_match_power8; - pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06; + pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; + pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; pcc->init_proc = init_proc_POWER8; pcc->check_pow = check_pow_nocheck; pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | From 52b2519c4ea9a6aa4df7abfe35fd1755c5c8546c Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Tue, 7 Jun 2016 17:39:38 +0200 Subject: [PATCH 3/8] ppc: Provide function to get CPU class of the host CPU When running with KVM, we might be interested in some details of the host CPU class, too, so provide a function to get the corresponding CPU class. Signed-off-by: Thomas Huth Reviewed-by: Michael Roth Signed-off-by: David Gibson --- target-ppc/kvm.c | 19 ++++++++++++++----- target-ppc/kvm_ppc.h | 7 +++++++ 2 files changed, 21 insertions(+), 5 deletions(-) diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c index 24d6032007..6c153611c0 100644 --- a/target-ppc/kvm.c +++ b/target-ppc/kvm.c @@ -2329,6 +2329,19 @@ static PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc) return POWERPC_CPU_CLASS(oc); } +PowerPCCPUClass *kvm_ppc_get_host_cpu_class(void) +{ + uint32_t host_pvr = mfpvr(); + PowerPCCPUClass *pvr_pcc; + + pvr_pcc = ppc_cpu_class_by_pvr(host_pvr); + if (pvr_pcc == NULL) { + pvr_pcc = ppc_cpu_class_by_pvr_mask(host_pvr); + } + + return pvr_pcc; +} + static int kvm_ppc_register_host_cpu_type(void) { TypeInfo type_info = { @@ -2336,14 +2349,10 @@ static int kvm_ppc_register_host_cpu_type(void) .instance_init = kvmppc_host_cpu_initfn, .class_init = kvmppc_host_cpu_class_init, }; - uint32_t host_pvr = mfpvr(); PowerPCCPUClass *pvr_pcc; DeviceClass *dc; - pvr_pcc = ppc_cpu_class_by_pvr(host_pvr); - if (pvr_pcc == NULL) { - pvr_pcc = ppc_cpu_class_by_pvr_mask(host_pvr); - } + pvr_pcc = kvm_ppc_get_host_cpu_class(); if (pvr_pcc == NULL) { return -1; } diff --git a/target-ppc/kvm_ppc.h b/target-ppc/kvm_ppc.h index 3b2090e42e..20bfb59b1a 100644 --- a/target-ppc/kvm_ppc.h +++ b/target-ppc/kvm_ppc.h @@ -56,6 +56,7 @@ void kvmppc_hash64_write_pte(CPUPPCState *env, target_ulong pte_index, bool kvmppc_has_cap_fixup_hcalls(void); int kvmppc_enable_hwrng(void); int kvmppc_put_books_sregs(PowerPCCPU *cpu); +PowerPCCPUClass *kvm_ppc_get_host_cpu_class(void); #else @@ -252,6 +253,12 @@ static inline int kvmppc_put_books_sregs(PowerPCCPU *cpu) { abort(); } + +static inline PowerPCCPUClass *kvm_ppc_get_host_cpu_class(void) +{ + return NULL; +} + #endif #ifndef CONFIG_KVM From eac4fba965136f61cc239a450bec12adcef6b449 Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Tue, 7 Jun 2016 17:39:39 +0200 Subject: [PATCH 4/8] ppc: Improve PCR bit selection in ppc_set_compat() When using an olderr PowerISA level, all the upper compatibility bits have to be enabled, too. For example when we want to run something in PowerISA 2.05 compatibility mode on POWER8, the bit for 2.06 has to be set beside the bit for 2.05. Additionally, to make sure that we do not set bits that are not supported by the host, we apply a mask with the known-to-be-good bits here, too. Signed-off-by: Thomas Huth [dwg: Added some #ifs to fix compile on 32-bit targets] Signed-off-by: David Gibson --- target-ppc/cpu.h | 2 ++ target-ppc/translate_init.c | 15 +++++++++++---- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 9087a08002..93c2dd5a65 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1187,7 +1187,9 @@ void ppc_store_msr (CPUPPCState *env, target_ulong value); void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf); int ppc_get_compat_smt_threads(PowerPCCPU *cpu); +#if defined(TARGET_PPC64) void ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version, Error **errp); +#endif /* Time-base and decrementer management */ #ifndef NO_CPU_IO_DEFS diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index fa09183f2f..274009a888 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -9515,28 +9515,34 @@ int ppc_get_compat_smt_threads(PowerPCCPU *cpu) return ret; } +#ifdef TARGET_PPC64 void ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version, Error **errp) { int ret = 0; CPUPPCState *env = &cpu->env; + PowerPCCPUClass *host_pcc; cpu->cpu_version = cpu_version; switch (cpu_version) { case CPU_POWERPC_LOGICAL_2_05: - env->spr[SPR_PCR] = PCR_COMPAT_2_05; + env->spr[SPR_PCR] = PCR_TM_DIS | PCR_VSX_DIS | PCR_COMPAT_2_07 | + PCR_COMPAT_2_06 | PCR_COMPAT_2_05; break; case CPU_POWERPC_LOGICAL_2_06: - env->spr[SPR_PCR] = PCR_COMPAT_2_06; - break; case CPU_POWERPC_LOGICAL_2_06_PLUS: - env->spr[SPR_PCR] = PCR_COMPAT_2_06; + env->spr[SPR_PCR] = PCR_TM_DIS | PCR_COMPAT_2_07 | PCR_COMPAT_2_06; break; default: env->spr[SPR_PCR] = 0; break; } + host_pcc = kvm_ppc_get_host_cpu_class(); + if (host_pcc) { + env->spr[SPR_PCR] &= host_pcc->pcr_mask; + } + if (kvm_enabled()) { ret = kvmppc_set_compat(cpu, cpu->cpu_version); if (ret < 0) { @@ -9545,6 +9551,7 @@ void ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version, Error **errp) } } } +#endif static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b) { From b30ff227c27c931155f768a04c44a6c8757f195f Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Tue, 7 Jun 2016 17:39:40 +0200 Subject: [PATCH 5/8] ppc: Add PowerISA 2.07 compatibility mode Make sure that guests can use the PowerISA 2.07 CPU sPAPR compatibility mode when they request it and the target CPU supports it. Signed-off-by: Thomas Huth Signed-off-by: David Gibson --- hw/ppc/spapr_hcall.c | 6 ++++-- target-ppc/translate_init.c | 3 +++ 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index cc16249a8c..2ba5cbdb19 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -927,7 +927,7 @@ static void cas_handle_compat_cpu(PowerPCCPUClass *pcc, uint32_t pvr, unsigned *cpu_version) { unsigned lvl = get_compat_level(pvr); - bool is205, is206; + bool is205, is206, is207; if (!lvl) { return; @@ -939,8 +939,10 @@ static void cas_handle_compat_cpu(PowerPCCPUClass *pcc, uint32_t pvr, is206 = (pcc->pcr_supported & PCR_COMPAT_2_06) && ((lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_06)) || (lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_06_PLUS))); + is207 = (pcc->pcr_supported & PCR_COMPAT_2_07) && + (lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_07)); - if (is205 || is206) { + if (is205 || is206 || is207) { if (!max_lvl) { /* User did not set the level, choose the highest */ if (*compat_lvl <= lvl) { diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 274009a888..ca894ff4af 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -9533,6 +9533,9 @@ void ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version, Error **errp) case CPU_POWERPC_LOGICAL_2_06_PLUS: env->spr[SPR_PCR] = PCR_TM_DIS | PCR_COMPAT_2_07 | PCR_COMPAT_2_06; break; + case CPU_POWERPC_LOGICAL_2_07: + env->spr[SPR_PCR] = PCR_COMPAT_2_07; + break; default: env->spr[SPR_PCR] = 0; break; From 42bff4772ef96d901772240b10eda6d66ef771a1 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Tue, 7 Jun 2016 22:28:42 +1000 Subject: [PATCH 6/8] Add PowerPC AT_HWCAP2 definitions We need the PPC_FEATURE2_HAS_HTM bit in a subsequent patch, so add the PowerPC AT_HWCAP2 definitions. Signed-off-by: Anton Blanchard Signed-off-by: David Gibson --- include/elf.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/include/elf.h b/include/elf.h index 28d448bbcc..8533b2a8b0 100644 --- a/include/elf.h +++ b/include/elf.h @@ -477,6 +477,19 @@ typedef struct { #define PPC_FEATURE_TRUE_LE 0x00000002 #define PPC_FEATURE_PPC_LE 0x00000001 +/* Bits present in AT_HWCAP2 for PowerPC. */ + +#define PPC_FEATURE2_ARCH_2_07 0x80000000 +#define PPC_FEATURE2_HAS_HTM 0x40000000 +#define PPC_FEATURE2_HAS_DSCR 0x20000000 +#define PPC_FEATURE2_HAS_EBB 0x10000000 +#define PPC_FEATURE2_HAS_ISEL 0x08000000 +#define PPC_FEATURE2_HAS_TAR 0x04000000 +#define PPC_FEATURE2_HAS_VEC_CRYPTO 0x02000000 +#define PPC_FEATURE2_HTM_NOSC 0x01000000 +#define PPC_FEATURE2_ARCH_3_00 0x00800000 +#define PPC_FEATURE2_HAS_IEEE128 0x00400000 + /* Bits present in AT_HWCAP for Sparc. */ #define HWCAP_SPARC_FLUSH 0x00000001 From bc9ca5958d084222cdb233619dfc5046c81fb76d Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Fri, 10 Jun 2016 19:26:37 +0100 Subject: [PATCH 7/8] macio: call dma_memory_unmap() at the end of each DMA transfer This ensures that the underlying memory is marked dirty once the transfer is complete and resolves cache coherency problems under MacOS 9. Signed-off-by: Mark Cave-Ayland Signed-off-by: David Gibson --- hw/ide/macio.c | 46 +++++++++++++++++++++----------------- include/hw/ppc/mac_dbdma.h | 5 +++++ 2 files changed, 31 insertions(+), 20 deletions(-) diff --git a/hw/ide/macio.c b/hw/ide/macio.c index 78c10a0406..fa57352fc8 100644 --- a/hw/ide/macio.c +++ b/hw/ide/macio.c @@ -66,8 +66,7 @@ static void pmac_dma_read(BlockBackend *blk, DBDMA_io *io = opaque; MACIOIDEState *m = io->opaque; IDEState *s = idebus_active_if(&m->bus); - dma_addr_t dma_addr, dma_len; - void *mem; + dma_addr_t dma_addr; int64_t sector_num; int nsector; uint64_t align = BDRV_SECTOR_SIZE; @@ -84,9 +83,10 @@ static void pmac_dma_read(BlockBackend *blk, sector_num, nsector); dma_addr = io->addr; - dma_len = io->len; - mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len, - DMA_DIRECTION_FROM_DEVICE); + io->dir = DMA_DIRECTION_FROM_DEVICE; + io->dma_len = io->len; + io->dma_mem = dma_memory_map(&address_space_memory, dma_addr, &io->dma_len, + io->dir); if (offset & (align - 1)) { head_bytes = offset & (align - 1); @@ -100,7 +100,7 @@ static void pmac_dma_read(BlockBackend *blk, offset = offset & ~(align - 1); } - qemu_iovec_add(&io->iov, mem, io->len); + qemu_iovec_add(&io->iov, io->dma_mem, io->len); if ((offset + bytes) & (align - 1)) { tail_bytes = (offset + bytes) & (align - 1); @@ -130,8 +130,7 @@ static void pmac_dma_write(BlockBackend *blk, DBDMA_io *io = opaque; MACIOIDEState *m = io->opaque; IDEState *s = idebus_active_if(&m->bus); - dma_addr_t dma_addr, dma_len; - void *mem; + dma_addr_t dma_addr; int64_t sector_num; int nsector; uint64_t align = BDRV_SECTOR_SIZE; @@ -149,9 +148,10 @@ static void pmac_dma_write(BlockBackend *blk, sector_num, nsector); dma_addr = io->addr; - dma_len = io->len; - mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len, - DMA_DIRECTION_TO_DEVICE); + io->dir = DMA_DIRECTION_TO_DEVICE; + io->dma_len = io->len; + io->dma_mem = dma_memory_map(&address_space_memory, dma_addr, &io->dma_len, + io->dir); if (offset & (align - 1)) { head_bytes = offset & (align - 1); @@ -163,7 +163,7 @@ static void pmac_dma_write(BlockBackend *blk, blk_pread(s->blk, (sector_num << 9), &io->head_remainder, align); qemu_iovec_add(&io->iov, &io->head_remainder, head_bytes); - qemu_iovec_add(&io->iov, mem, io->len); + qemu_iovec_add(&io->iov, io->dma_mem, io->len); bytes += offset & (align - 1); offset = offset & ~(align - 1); @@ -181,7 +181,7 @@ static void pmac_dma_write(BlockBackend *blk, blk_pread(s->blk, (sector_num << 9), &io->tail_remainder, align); if (!unaligned_head) { - qemu_iovec_add(&io->iov, mem, io->len); + qemu_iovec_add(&io->iov, io->dma_mem, io->len); } qemu_iovec_add(&io->iov, &io->tail_remainder + tail_bytes, @@ -193,7 +193,7 @@ static void pmac_dma_write(BlockBackend *blk, } if (!unaligned_head && !unaligned_tail) { - qemu_iovec_add(&io->iov, mem, io->len); + qemu_iovec_add(&io->iov, io->dma_mem, io->len); } s->io_buffer_size -= io->len; @@ -214,18 +214,18 @@ static void pmac_dma_trim(BlockBackend *blk, DBDMA_io *io = opaque; MACIOIDEState *m = io->opaque; IDEState *s = idebus_active_if(&m->bus); - dma_addr_t dma_addr, dma_len; - void *mem; + dma_addr_t dma_addr; qemu_iovec_destroy(&io->iov); qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1); dma_addr = io->addr; - dma_len = io->len; - mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len, - DMA_DIRECTION_TO_DEVICE); + io->dir = DMA_DIRECTION_TO_DEVICE; + io->dma_len = io->len; + io->dma_mem = dma_memory_map(&address_space_memory, dma_addr, &io->dma_len, + io->dir); - qemu_iovec_add(&io->iov, mem, io->len); + qemu_iovec_add(&io->iov, io->dma_mem, io->len); s->io_buffer_size -= io->len; s->io_buffer_index += io->len; io->len = 0; @@ -285,6 +285,9 @@ static void pmac_ide_atapi_transfer_cb(void *opaque, int ret) return; done: + dma_memory_unmap(&address_space_memory, io->dma_mem, io->dma_len, + io->dir, io->dma_len); + if (ret < 0) { block_acct_failed(blk_get_stats(s->blk), &s->acct); } else { @@ -351,6 +354,9 @@ static void pmac_ide_transfer_cb(void *opaque, int ret) return; done: + dma_memory_unmap(&address_space_memory, io->dma_mem, io->dma_len, + io->dir, io->dma_len); + if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) { if (ret < 0) { block_acct_failed(blk_get_stats(s->blk), &s->acct); diff --git a/include/hw/ppc/mac_dbdma.h b/include/hw/ppc/mac_dbdma.h index 0cce4e8bb4..d15a6ccf3e 100644 --- a/include/hw/ppc/mac_dbdma.h +++ b/include/hw/ppc/mac_dbdma.h @@ -24,6 +24,7 @@ #include "exec/memory.h" #include "qemu/iov.h" +#include "sysemu/dma.h" typedef struct DBDMA_io DBDMA_io; @@ -44,6 +45,10 @@ struct DBDMA_io { uint8_t head_remainder[0x200]; uint8_t tail_remainder[0x200]; QEMUIOVector iov; + /* DMA request */ + void *dma_mem; + dma_addr_t dma_len; + DMADirection dir; }; /* From d0e5a8f2937de66778d94c20a8fc5cf43501fa04 Mon Sep 17 00:00:00 2001 From: Bharata B Rao Date: Fri, 10 Jun 2016 10:44:48 +0530 Subject: [PATCH 8/8] spapr: Ensure all LMBs are represented in ibm,dynamic-memory Memory hotplug can fail for some combinations of RAM and maxmem when DDW is enabled in the presence of devices like nec-usb-xhci. DDW depends on maximum addressable memory returned by guest and this value is currently being calculated wrongly by the guest kernel routine memory_hotplug_max(). While there is an attempt to fix the guest kernel, this patch works around the problem within QEMU itself. memory_hotplug_max() routine in the guest kernel arrives at max addressable memory by multiplying lmb-size with the lmb-count obtained from ibm,dynamic-memory property. There are two assumptions here: - All LMBs are part of ibm,dynamic memory: This is not true for PowerKVM where only hot-pluggable LMBs are present in this property. - The memory area comprising of RAM and hotplug region is contiguous: This needn't be true always for PowerKVM as there can be gap between boot time RAM and hotplug region. To work around this guest kernel bug, ensure that ibm,dynamic-memory has information about all the LMBs (RMA, boot-time LMBs, future hotpluggable LMBs, and dummy LMBs to cover the gap between RAM and hotpluggable region). RMA is represented separately by memory@0 node. Hence mark RMA LMBs and also the LMBs for the gap b/n RAM and hotpluggable region as reserved and as having no valid DRC so that these LMBs are not considered by the guest. Signed-off-by: Bharata B Rao Reviewed-by: Michael Roth Reviewed-by: Nathan Fontenot Signed-off-by: David Gibson --- hw/ppc/spapr.c | 55 +++++++++++++++++++++++++++--------------- include/hw/ppc/spapr.h | 6 +++-- 2 files changed, 40 insertions(+), 21 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 0636642341..9a4a803b17 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -762,14 +762,17 @@ static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) int ret, i, offset; uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; - uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; + uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; + uint32_t nr_lmbs = (spapr->hotplug_memory.base + + memory_region_size(&spapr->hotplug_memory.mr)) / + lmb_size; uint32_t *int_buf, *cur_index, buf_len; int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; /* - * Don't create the node if there are no DR LMBs. + * Don't create the node if there is no hotpluggable memory */ - if (!nr_lmbs) { + if (machine->ram_size == machine->maxram_size) { return 0; } @@ -803,26 +806,40 @@ static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) int_buf[0] = cpu_to_be32(nr_lmbs); cur_index++; for (i = 0; i < nr_lmbs; i++) { - sPAPRDRConnector *drc; - sPAPRDRConnectorClass *drck; - uint64_t addr = i * lmb_size + spapr->hotplug_memory.base;; + uint64_t addr = i * lmb_size; uint32_t *dynamic_memory = cur_index; - drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, - addr/lmb_size); - g_assert(drc); - drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); + if (i >= hotplug_lmb_start) { + sPAPRDRConnector *drc; + sPAPRDRConnectorClass *drck; - dynamic_memory[0] = cpu_to_be32(addr >> 32); - dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); - dynamic_memory[2] = cpu_to_be32(drck->get_index(drc)); - dynamic_memory[3] = cpu_to_be32(0); /* reserved */ - dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); - if (addr < machine->ram_size || - memory_region_present(get_system_memory(), addr)) { - dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); + drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i); + g_assert(drc); + drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); + + dynamic_memory[0] = cpu_to_be32(addr >> 32); + dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); + dynamic_memory[2] = cpu_to_be32(drck->get_index(drc)); + dynamic_memory[3] = cpu_to_be32(0); /* reserved */ + dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); + if (memory_region_present(get_system_memory(), addr)) { + dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); + } else { + dynamic_memory[5] = cpu_to_be32(0); + } } else { - dynamic_memory[5] = cpu_to_be32(0); + /* + * LMB information for RMA, boot time RAM and gap b/n RAM and + * hotplug memory region -- all these are marked as reserved + * and as having no valid DRC. + */ + dynamic_memory[0] = cpu_to_be32(addr >> 32); + dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); + dynamic_memory[2] = cpu_to_be32(0); + dynamic_memory[3] = cpu_to_be32(0); /* reserved */ + dynamic_memory[4] = cpu_to_be32(-1); + dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | + SPAPR_LMB_FLAGS_DRC_INVALID); } cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 971df3d0df..3ac85c07d7 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -620,9 +620,11 @@ int spapr_rng_populate_dt(void *fdt); #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 /* - * This flag value defines the LMB as assigned in ibm,dynamic-memory - * property under ibm,dynamic-reconfiguration-memory node. + * Defines for flag value in ibm,dynamic-memory property under + * ibm,dynamic-reconfiguration-memory node. */ #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 +#define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 +#define SPAPR_LMB_FLAGS_RESERVED 0x00000080 #endif /* !defined (__HW_SPAPR_H__) */