elfload: fix size of registers for N32
Registers are 64-bit in size for the MIPS n32 ABI. Define target_elf_greg_t accordingly, and use the correct function to do endian swaps. Reviewed-by: Peter Maydell <peter.maydell@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
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@ -101,7 +101,14 @@ enum {
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#define ELF_DATA ELFDATA2LSB
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#endif
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#ifdef TARGET_ABI_MIPSN32
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typedef target_ulong target_elf_greg_t;
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#define tswapreg(ptr) tswapl(ptr)
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#else
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typedef abi_ulong target_elf_greg_t;
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#define tswapreg(ptr) tswapal(ptr)
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#endif
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#ifdef USE_UID16
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typedef target_ushort target_uid_t;
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typedef target_ushort target_gid_t;
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@ -747,17 +754,17 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUMIPSState *e
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(*regs)[TARGET_EF_R0] = 0;
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for (i = 1; i < ARRAY_SIZE(env->active_tc.gpr); i++) {
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(*regs)[TARGET_EF_R0 + i] = tswapl(env->active_tc.gpr[i]);
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(*regs)[TARGET_EF_R0 + i] = tswapreg(env->active_tc.gpr[i]);
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}
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(*regs)[TARGET_EF_R26] = 0;
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(*regs)[TARGET_EF_R27] = 0;
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(*regs)[TARGET_EF_LO] = tswapl(env->active_tc.LO[0]);
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(*regs)[TARGET_EF_HI] = tswapl(env->active_tc.HI[0]);
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(*regs)[TARGET_EF_CP0_EPC] = tswapl(env->active_tc.PC);
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(*regs)[TARGET_EF_CP0_BADVADDR] = tswapl(env->CP0_BadVAddr);
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(*regs)[TARGET_EF_CP0_STATUS] = tswapl(env->CP0_Status);
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(*regs)[TARGET_EF_CP0_CAUSE] = tswapl(env->CP0_Cause);
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(*regs)[TARGET_EF_LO] = tswapreg(env->active_tc.LO[0]);
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(*regs)[TARGET_EF_HI] = tswapreg(env->active_tc.HI[0]);
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(*regs)[TARGET_EF_CP0_EPC] = tswapreg(env->active_tc.PC);
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(*regs)[TARGET_EF_CP0_BADVADDR] = tswapreg(env->CP0_BadVAddr);
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(*regs)[TARGET_EF_CP0_STATUS] = tswapreg(env->CP0_Status);
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(*regs)[TARGET_EF_CP0_CAUSE] = tswapreg(env->CP0_Cause);
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}
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#define USE_ELF_CORE_DUMP
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