target/ppc: Implement vclzdm/vctzdm instructions
The signature of do_cntzdm is changed to allow reuse as GVecGen3i.fni8. The method is also moved out of #ifdef TARGET_PPC64, as PowerISA doesn't say vclzdm and vctzdm are 64-bit only. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Luis Pires <luis.pires@eldorado.org.br> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20211104123719.323713-3-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -334,3 +334,5 @@ DSCRIQ 111111 ..... ..... ...... 001100010 . @Z22_tap_sh_rc
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## Vector Bit Manipulation Instruction
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## Vector Bit Manipulation Instruction
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VCFUGED 000100 ..... ..... ..... 10101001101 @VX
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VCFUGED 000100 ..... ..... ..... 10101001101 @VX
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VCLZDM 000100 ..... ..... ..... 11110000100 @VX
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VCTZDM 000100 ..... ..... ..... 11111000100 @VX
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@ -414,8 +414,7 @@ static bool trans_CFUGED(DisasContext *ctx, arg_X *a)
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return true;
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return true;
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}
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}
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#if defined(TARGET_PPC64)
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static void do_cntzdm(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 mask, int64_t trail)
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static void do_cntzdm(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 mask, bool trail)
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{
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{
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TCGv_i64 tmp;
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TCGv_i64 tmp;
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TCGLabel *l1;
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TCGLabel *l1;
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@ -444,7 +443,6 @@ static void do_cntzdm(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 mask, bool trail)
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tcg_gen_mov_i64(dst, tmp);
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tcg_gen_mov_i64(dst, tmp);
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}
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}
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#endif
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static bool trans_CNTLZDM(DisasContext *ctx, arg_X *a)
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static bool trans_CNTLZDM(DisasContext *ctx, arg_X *a)
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{
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{
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@ -1575,6 +1575,38 @@ static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a)
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return true;
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return true;
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}
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}
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static bool trans_VCLZDM(DisasContext *ctx, arg_VX *a)
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{
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static const GVecGen3i g = {
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.fni8 = do_cntzdm,
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.vece = MO_64,
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};
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REQUIRE_INSNS_FLAGS2(ctx, ISA310);
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REQUIRE_VECTOR(ctx);
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tcg_gen_gvec_3i(avr_full_offset(a->vrt), avr_full_offset(a->vra),
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avr_full_offset(a->vrb), 16, 16, false, &g);
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return true;
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}
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static bool trans_VCTZDM(DisasContext *ctx, arg_VX *a)
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{
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static const GVecGen3i g = {
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.fni8 = do_cntzdm,
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.vece = MO_64,
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};
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REQUIRE_INSNS_FLAGS2(ctx, ISA310);
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REQUIRE_VECTOR(ctx);
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tcg_gen_gvec_3i(avr_full_offset(a->vrt), avr_full_offset(a->vra),
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avr_full_offset(a->vrb), 16, 16, true, &g);
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return true;
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}
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#undef GEN_VR_LDX
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#undef GEN_VR_LDX
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#undef GEN_VR_STX
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#undef GEN_VR_STX
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#undef GEN_VR_LVE
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#undef GEN_VR_LVE
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