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s390x/tcg: Implement 32/128 bit for VECTOR FP TEST DATA CLASS IMMEDIATE 

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20210608092337.12221-21-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
This commit is contained in:
David Hildenbrand 2021-06-08 11:23:31 +02:00 committed by Cornelia Huck
parent 390eeb3575
commit a38b5a0eab
3 changed files with 70 additions and 2 deletions
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2
target/s390x/helper.h
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@ -299,7 +299,9 @@ DEF_HELPER_FLAGS_4(gvec_vfsq128, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfs32, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfs64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfs128, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_4(gvec_vftci32, void, ptr, cptr, env, i32)
DEF_HELPER_4(gvec_vftci64, void, ptr, cptr, env, i32)
DEF_HELPER_4(gvec_vftci128, void, ptr, cptr, env, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)

23
target/s390x/translate_vx.c.inc
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@ -2965,14 +2965,33 @@ static DisasJumpType op_vftci(DisasContext *s, DisasOps *o)
const uint16_t i3 = get_field(s, i3);
const uint8_t fpf = get_field(s, m4);
const uint8_t m5 = get_field(s, m5);
gen_helper_gvec_2_ptr *fn = NULL;
if (fpf != FPF_LONG || extract32(m5, 0, 3)) {
switch (fpf) {
case FPF_SHORT:
if (s390_has_feat(S390_FEAT_VECTOR_ENH)) {
fn = gen_helper_gvec_vftci32;
}
break;
case FPF_LONG:
fn = gen_helper_gvec_vftci64;
break;
case FPF_EXT:
if (s390_has_feat(S390_FEAT_VECTOR_ENH)) {
fn = gen_helper_gvec_vftci128;
}
break;
default:
break;
}
if (!fn || extract32(m5, 0, 3)) {
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env,
deposit32(m5, 4, 12, i3), gen_helper_gvec_vftci64);
deposit32(m5, 4, 12, i3), fn);
set_cc_static(s);
return DISAS_NEXT;
}

47
target/s390x/vec_fpu_helper.c
View File

@ -622,6 +622,36 @@ void HELPER(gvec_##NAME##BITS)(void *v1, const void *v2, const void *v3, \
DEF_GVEC_VFMA(vfma, 0)
DEF_GVEC_VFMA(vfms, float_muladd_negate_c)
void HELPER(gvec_vftci32)(void *v1, const void *v2, CPUS390XState *env,
uint32_t desc)
{
uint16_t i3 = extract32(simd_data(desc), 4, 12);
bool s = extract32(simd_data(desc), 3, 1);
int i, match = 0;
for (i = 0; i < 4; i++) {
float32 a = s390_vec_read_float32(v2, i);
if (float32_dcmask(env, a) & i3) {
match++;
s390_vec_write_element32(v1, i, -1u);
} else {
s390_vec_write_element32(v1, i, 0);
}
if (s) {
break;
}
}
if (match == 4 || (s && match)) {
env->cc_op = 0;
} else if (match) {
env->cc_op = 1;
} else {
env->cc_op = 3;
}
}
void HELPER(gvec_vftci64)(void *v1, const void *v2, CPUS390XState *env,
uint32_t desc)
{
@ -651,3 +681,20 @@ void HELPER(gvec_vftci64)(void *v1, const void *v2, CPUS390XState *env,
env->cc_op = 3;
}
}
void HELPER(gvec_vftci128)(void *v1, const void *v2, CPUS390XState *env,
uint32_t desc)
{
const float128 a = s390_vec_read_float128(v2);
uint16_t i3 = extract32(simd_data(desc), 4, 12);
if (float128_dcmask(env, a) & i3) {
env->cc_op = 0;
s390_vec_write_element64(v1, 0, -1ull);
s390_vec_write_element64(v1, 1, -1ull);
} else {
env->cc_op = 3;
s390_vec_write_element64(v1, 0, 0);
s390_vec_write_element64(v1, 1, 0);
}
}