OpenE2K/qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

tcg: document double-word support opcodes.

Browse Source 
The internal opcodes brcond2, add2, sub2, mulu2 were undocumented.
Place these in a new section that clearly indicates that they are
not to be emitted by translators.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Richard Henderson 2010-01-07 10:07:35 -08:00 committed by Aurelien Jarno
parent fd7a446f16
commit a38e609c46
1 changed files with 23 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
tcg/README
View File

@ -323,6 +323,29 @@ st32_i64 t0, t1, offset
write(t0, t1 + offset) write(t0, t1 + offset)
Write 8, 16, 32 or 64 bits to host memory. Write 8, 16, 32 or 64 bits to host memory.
********* 64-bit target on 32-bit host support
The following opcodes are internal to TCG. Thus they are to be implemented by
32-bit host code generators, but are not to be emitted by guest translators.
They are emitted as needed by inline functions within "tcg-op.h".
* brcond2_i32 cond, t0_low, t0_high, t1_low, t1_high, label
Similar to brcond, except that the 64-bit values T0 and T1
are formed from two 32-bit arguments.
* add2_i32 t0_low, t0_high, t1_low, t1_high, t2_low, t2_high
* sub2_i32 t0_low, t0_high, t1_low, t1_high, t2_low, t2_high
Similar to add/sub, except that the 64-bit inputs T1 and T2 are
formed from two 32-bit arguments, and the 64-bit output T0
is returned in two 32-bit outputs.
* mulu2_i32 t0_low, t0_high, t1, t2
Similar to mul, except two 32-bit (unsigned) inputs T1 and T2 yielding
the full 64-bit product T0. The later is returned in two 32-bit outputs.
********* QEMU specific operations ********* QEMU specific operations
* tb_exit t0 * tb_exit t0