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qtest: Add functions for accessing devices on Aspeed I2C controller

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Add read and write functions for accessing registers of I2C devices
connected to the Aspeed I2C controller.

Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Ninad Palsule <ninad@linux.ibm.com>
Message-Id: <20230331173051.3857801-2-stefanb@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
This commit is contained in:
Stefan Berger 2023-03-31 13:30:49 -04:00 committed by Thomas Huth
parent 2243299a74
commit a3ebb580a2
3 changed files with 165 additions and 0 deletions
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7
include/hw/i2c/aspeed_i2c.h
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@ -38,6 +38,13 @@ OBJECT_DECLARE_TYPE(AspeedI2CState, AspeedI2CClass, ASPEED_I2C)
#define ASPEED_I2C_OLD_NUM_REG 11 #define ASPEED_I2C_OLD_NUM_REG 11
#define ASPEED_I2C_NEW_NUM_REG 22 #define ASPEED_I2C_NEW_NUM_REG 22
#define A_I2CD_M_STOP_CMD BIT(5)
#define A_I2CD_M_RX_CMD BIT(3)
#define A_I2CD_M_TX_CMD BIT(1)
#define A_I2CD_M_START_CMD BIT(0)
#define A_I2CD_MASTER_EN BIT(0)
/* Tx State Machine */ /* Tx State Machine */
#define I2CD_TX_STATE_MASK 0xf #define I2CD_TX_STATE_MASK 0xf
#define I2CD_IDLE 0x0 #define I2CD_IDLE 0x0

117
tests/qtest/qtest_aspeed.c Normal file
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@ -0,0 +1,117 @@
/*
* Aspeed i2c bus interface for reading from and writing to i2c device registers
*
* Copyright (c) 2023 IBM Corporation
*
* Authors:
* Stefan Berger <stefanb@linux.ibm.com>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#include "qemu/osdep.h"
#include "qtest_aspeed.h"
#include "hw/i2c/aspeed_i2c.h"
static void aspeed_i2c_startup(QTestState *s, uint32_t baseaddr,
uint8_t slave_addr, uint8_t reg)
{
uint32_t v;
static int once;
if (!once) {
/* one time: enable master */
qtest_writel(s, baseaddr + A_I2CC_FUN_CTRL, 0);
v = qtest_readl(s, baseaddr + A_I2CC_FUN_CTRL) | A_I2CD_MASTER_EN;
qtest_writel(s, baseaddr + A_I2CC_FUN_CTRL, v);
once = 1;
}
/* select device */
qtest_writel(s, baseaddr + A_I2CD_BYTE_BUF, slave_addr << 1);
qtest_writel(s, baseaddr + A_I2CD_CMD,
A_I2CD_M_START_CMD | A_I2CD_M_RX_CMD);
/* select the register to write to */
qtest_writel(s, baseaddr + A_I2CD_BYTE_BUF, reg);
qtest_writel(s, baseaddr + A_I2CD_CMD, A_I2CD_M_TX_CMD);
}
static uint32_t aspeed_i2c_read_n(QTestState *s,
uint32_t baseaddr, uint8_t slave_addr,
uint8_t reg, size_t nbytes)
{
uint32_t res = 0;
uint32_t v;
size_t i;
aspeed_i2c_startup(s, baseaddr, slave_addr, reg);
for (i = 0; i < nbytes; i++) {
qtest_writel(s, baseaddr + A_I2CD_CMD, A_I2CD_M_RX_CMD);
v = qtest_readl(s, baseaddr + A_I2CD_BYTE_BUF) >> 8;
res |= (v & 0xff) << (i * 8);
}
qtest_writel(s, baseaddr + A_I2CD_CMD, A_I2CD_M_STOP_CMD);
return res;
}
uint32_t aspeed_i2c_readl(QTestState *s,
uint32_t baseaddr, uint8_t slave_addr, uint8_t reg)
{
return aspeed_i2c_read_n(s, baseaddr, slave_addr, reg, sizeof(uint32_t));
}
uint16_t aspeed_i2c_readw(QTestState *s,
uint32_t baseaddr, uint8_t slave_addr, uint8_t reg)
{
return aspeed_i2c_read_n(s, baseaddr, slave_addr, reg, sizeof(uint16_t));
}
uint8_t aspeed_i2c_readb(QTestState *s,
uint32_t baseaddr, uint8_t slave_addr, uint8_t reg)
{
return aspeed_i2c_read_n(s, baseaddr, slave_addr, reg, sizeof(uint8_t));
}
static void aspeed_i2c_write_n(QTestState *s,
uint32_t baseaddr, uint8_t slave_addr,
uint8_t reg, uint32_t v, size_t nbytes)
{
size_t i;
aspeed_i2c_startup(s, baseaddr, slave_addr, reg);
for (i = 0; i < nbytes; i++) {
qtest_writel(s, baseaddr + A_I2CD_BYTE_BUF, v & 0xff);
v >>= 8;
qtest_writel(s, baseaddr + A_I2CD_CMD, A_I2CD_M_TX_CMD);
}
qtest_writel(s, baseaddr + A_I2CD_CMD, A_I2CD_M_STOP_CMD);
}
void aspeed_i2c_writel(QTestState *s,
uint32_t baseaddr, uint8_t slave_addr,
uint8_t reg, uint32_t v)
{
aspeed_i2c_write_n(s, baseaddr, slave_addr, reg, v, sizeof(v));
}
void aspeed_i2c_writew(QTestState *s,
uint32_t baseaddr, uint8_t slave_addr,
uint8_t reg, uint16_t v)
{
aspeed_i2c_write_n(s, baseaddr, slave_addr, reg, v, sizeof(v));
}
void aspeed_i2c_writeb(QTestState *s,
uint32_t baseaddr, uint8_t slave_addr,
uint8_t reg, uint8_t v)
{
aspeed_i2c_write_n(s, baseaddr, slave_addr, reg, v, sizeof(v));
}

41
tests/qtest/qtest_aspeed.h Normal file
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@ -0,0 +1,41 @@
/*
* Aspeed i2c bus interface to reading and writing to i2c device registers
*
* Copyright (c) 2023 IBM Corporation
*
* Authors:
* Stefan Berger <stefanb@linux.ibm.com>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#ifndef QTEST_ASPEED_H
#define QTEST_ASPEED_H
#include <stdint.h>
#include "libqtest.h"
#define AST2600_ASPEED_I2C_BASE_ADDR 0x1e78a000
/* Implements only AST2600 I2C controller */
static inline uint32_t ast2600_i2c_calc_bus_addr(uint8_t bus_num)
{
return AST2600_ASPEED_I2C_BASE_ADDR + 0x80 + bus_num * 0x80;
}
uint8_t aspeed_i2c_readb(QTestState *s,
uint32_t baseaddr, uint8_t slave_addr, uint8_t reg);
uint16_t aspeed_i2c_readw(QTestState *s,
uint32_t baseaddr, uint8_t slave_addr, uint8_t reg);
uint32_t aspeed_i2c_readl(QTestState *s,
uint32_t baseaddr, uint8_t slave_addr, uint8_t reg);
void aspeed_i2c_writeb(QTestState *s, uint32_t baseaddr, uint8_t slave_addr,
uint8_t reg, uint8_t v);
void aspeed_i2c_writew(QTestState *s, uint32_t baseaddr, uint8_t slave_addr,
uint8_t reg, uint16_t v);
void aspeed_i2c_writel(QTestState *s, uint32_t baseaddr, uint8_t slave_addr,
uint8_t reg, uint32_t v);
#endif