OpenE2K/qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

target/microblaze: gdb: Extend the number of registers presented to GDB

Browse Source 
Increase the number of Microblaze registers QEMU will report when
talking to GDB.

Signed-off-by: Joe Komlodi <komlodi@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-Id: <1589393329-223076-2-git-send-email-komlodi@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
This commit is contained in:
Joe Komlodi 2020-05-13 11:08:46 -07:00 committed by Edgar E. Iglesias
parent 2016a6a765
commit a44e82db0c
2 changed files with 50 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
target/microblaze/cpu.c
View File

@ -329,7 +329,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
#endif
dc->vmsd = &vmstate_mb_cpu;
device_class_set_props(dc, mb_properties);
cc->gdb_num_core_regs = 32 + 5;
cc->gdb_num_core_regs = 32 + 27;
cc->disas_set_info = mb_disas_set_info;
cc->tcg_initialize = mb_tcg_init;

52
target/microblaze/gdbstub.c
View File

@ -26,12 +26,37 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
CPUMBState *env = &cpu->env;
/*
* GDB expects registers to be reported in this order:
* R0-R31
* PC-BTR
* PVR0-PVR11
* EDR-TLBHI
* SLR-SHR
*/
if (n < 32) {
return gdb_get_reg32(mem_buf, env->regs[n]);
} else {
return gdb_get_reg32(mem_buf, env->sregs[n - 32]);
n -= 32;
switch (n) {
case 0 ... 5:
return gdb_get_reg32(mem_buf, env->sregs[n]);
/* PVR12 is intentionally skipped */
case 6 ... 17:
n -= 6;
return gdb_get_reg32(mem_buf, env->pvr.regs[n]);
case 18 ... 24:
/* Add an offset of 6 to resume where we left off with SRegs */
n = n - 18 + 6;
return gdb_get_reg32(mem_buf, env->sregs[n]);
case 25:
return gdb_get_reg32(mem_buf, env->slr);
case 26:
return gdb_get_reg32(mem_buf, env->shr);
default:
return 0;
}
}
return 0;
}
int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
@ -50,7 +75,28 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
if (n < 32) {
env->regs[n] = tmp;
} else {
env->sregs[n - 32] = tmp;
n -= 32;
switch (n) {
case 0 ... 5:
env->sregs[n] = tmp;
break;
/* PVR12 is intentionally skipped */
case 6 ... 17:
n -= 6;
env->pvr.regs[n] = tmp;
break;
case 18 ... 24:
/* Add an offset of 6 to resume where we left off with SRegs */
n = n - 18 + 6;
env->sregs[n] = tmp;
break;
case 25:
env->slr = tmp;
break;
case 26:
env->shr = tmp;
break;
}
}
return 4;
}