target/arm: Implement MVE LETP insn
Implement the MVE LETP insn. This is like the existing LE loop-end insn, but it must perform an FPU-enabled check, and on loop-exit it resets LTPSIZE to 4. To accommodate the requirement to do something on loop-exit, we drop the use of condlabel and instead manage both the TB exits manually, in the same way we already do in trans_WLS(). The other MVE-specific change to the LE insn is that we must raise an INVSTATE UsageFault insn if LTPSIZE is not 4. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210614151007.4545-10-peter.maydell@linaro.org
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@ -674,7 +674,7 @@ BL 1111 0. .......... 11.1 ............ @branch24
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DLS 1111 0 0000 100 rn:4 1110 0000 0000 0001 size=4
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DLS 1111 0 0000 100 rn:4 1110 0000 0000 0001 size=4
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WLS 1111 0 0000 100 rn:4 1100 . .......... 1 imm=%lob_imm size=4
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WLS 1111 0 0000 100 rn:4 1100 . .......... 1 imm=%lob_imm size=4
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{
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{
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LE 1111 0 0000 0 f:1 0 1111 1100 . .......... 1 imm=%lob_imm
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LE 1111 0 0000 0 f:1 tp:1 1111 1100 . .......... 1 imm=%lob_imm
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# This is WLSTP
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# This is WLSTP
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WLS 1111 0 0000 0 size:2 rn:4 1100 . .......... 1 imm=%lob_imm
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WLS 1111 0 0000 0 size:2 rn:4 1100 . .......... 1 imm=%lob_imm
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}
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}
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@ -8223,25 +8223,113 @@ static bool trans_LE(DisasContext *s, arg_LE *a)
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* any faster.
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* any faster.
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*/
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*/
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TCGv_i32 tmp;
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TCGv_i32 tmp;
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TCGLabel *loopend;
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bool fpu_active;
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if (!dc_isar_feature(aa32_lob, s)) {
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if (!dc_isar_feature(aa32_lob, s)) {
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return false;
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return false;
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}
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}
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if (a->f && a->tp) {
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return false;
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}
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if (s->condexec_mask) {
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/*
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* LE in an IT block is CONSTRAINED UNPREDICTABLE;
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* we choose to UNDEF, because otherwise our use of
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* gen_goto_tb(1) would clash with the use of TB exit 1
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* in the dc->condjmp condition-failed codepath in
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* arm_tr_tb_stop() and we'd get an assertion.
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*/
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return false;
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}
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if (a->tp) {
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/* LETP */
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if (!dc_isar_feature(aa32_mve, s)) {
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return false;
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}
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if (!vfp_access_check(s)) {
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s->eci_handled = true;
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return true;
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}
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}
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/* LE/LETP is OK with ECI set and leaves it untouched */
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/* LE/LETP is OK with ECI set and leaves it untouched */
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s->eci_handled = true;
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s->eci_handled = true;
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if (!a->f) {
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/*
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/* Not loop-forever. If LR <= 1 this is the last loop: do nothing. */
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* With MVE, LTPSIZE might not be 4, and we must emit an INVSTATE
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arm_gen_condlabel(s);
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* UsageFault exception for the LE insn in that case. Note that we
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tcg_gen_brcondi_i32(TCG_COND_LEU, cpu_R[14], 1, s->condlabel);
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* are not directly checking FPSCR.LTPSIZE but instead check the
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/* Decrement LR */
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* pseudocode LTPSIZE() function, which returns 4 if the FPU is
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tmp = load_reg(s, 14);
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* not currently active (ie ActiveFPState() returns false). We
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tcg_gen_addi_i32(tmp, tmp, -1);
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* can identify not-active purely from our TB state flags, as the
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store_reg(s, 14, tmp);
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* FPU is active only if:
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* the FPU is enabled
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* AND lazy state preservation is not active
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* AND we do not need a new fp context (this is the ASPEN/FPCA check)
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*
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* Usually we don't need to care about this distinction between
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* LTPSIZE and FPSCR.LTPSIZE, because the code in vfp_access_check()
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* will either take an exception or clear the conditions that make
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* the FPU not active. But LE is an unusual case of a non-FP insn
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* that looks at LTPSIZE.
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*/
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fpu_active = !s->fp_excp_el && !s->v7m_lspact && !s->v7m_new_fp_ctxt_needed;
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if (!a->tp && dc_isar_feature(aa32_mve, s) && fpu_active) {
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/* Need to do a runtime check for LTPSIZE != 4 */
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TCGLabel *skipexc = gen_new_label();
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tmp = load_cpu_field(v7m.ltpsize);
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tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 4, skipexc);
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tcg_temp_free_i32(tmp);
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gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
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default_exception_el(s));
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gen_set_label(skipexc);
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}
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if (a->f) {
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/* Loop-forever: just jump back to the loop start */
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gen_jmp(s, read_pc(s) - a->imm);
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return true;
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}
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/*
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* Not loop-forever. If LR <= loop-decrement-value this is the last loop.
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* For LE, we know at this point that LTPSIZE must be 4 and the
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* loop decrement value is 1. For LETP we need to calculate the decrement
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* value from LTPSIZE.
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*/
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loopend = gen_new_label();
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if (!a->tp) {
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tcg_gen_brcondi_i32(TCG_COND_LEU, cpu_R[14], 1, loopend);
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tcg_gen_addi_i32(cpu_R[14], cpu_R[14], -1);
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} else {
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/*
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* Decrement by 1 << (4 - LTPSIZE). We need to use a TCG local
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* so that decr stays live after the brcondi.
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*/
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TCGv_i32 decr = tcg_temp_local_new_i32();
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TCGv_i32 ltpsize = load_cpu_field(v7m.ltpsize);
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tcg_gen_sub_i32(decr, tcg_constant_i32(4), ltpsize);
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tcg_gen_shl_i32(decr, tcg_constant_i32(1), decr);
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tcg_temp_free_i32(ltpsize);
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tcg_gen_brcond_i32(TCG_COND_LEU, cpu_R[14], decr, loopend);
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tcg_gen_sub_i32(cpu_R[14], cpu_R[14], decr);
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tcg_temp_free_i32(decr);
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}
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}
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/* Jump back to the loop start */
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/* Jump back to the loop start */
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gen_jmp(s, read_pc(s) - a->imm);
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gen_jmp(s, read_pc(s) - a->imm);
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gen_set_label(loopend);
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if (a->tp) {
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/* Exits from tail-pred loops must reset LTPSIZE to 4 */
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tmp = tcg_const_i32(4);
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store_cpu_field(tmp, v7m.ltpsize);
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}
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/* End TB, continuing to following insn */
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gen_jmp_tb(s, s->base.pc_next, 1);
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return true;
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return true;
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}
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}
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