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ppc: implement xssqrtqp instruction 

xssqrtqp: VSX Scalar Square Root Quad-Precision.

Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Jose Ricardo Ziviani 2017-02-03 20:01:16 -02:00 committed by David Gibson
parent 917950d7f5
commit a4a68476de
4 changed files with 41 additions and 0 deletions
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38
target/ppc/fpu_helper.c
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@ -3392,3 +3392,41 @@ void helper_xsrqpxp(CPUPPCState *env, uint32_t opcode)
putVSR(rD(opcode) + 32, &xt, env);
float_check_status(env);
}
void helper_xssqrtqp(CPUPPCState *env, uint32_t opcode)
{
ppc_vsr_t xb;
ppc_vsr_t xt;
float_status tstat;
getVSR(rB(opcode) + 32, &xb, env);
memset(&xt, 0, sizeof(xt));
helper_reset_fpstatus(env);
if (unlikely(Rc(opcode) != 0)) {
/* TODO: Support xsadddpo after round-to-odd is implemented */
abort();
}
tstat = env->fp_status;
set_float_exception_flags(0, &tstat);
xt.f128 = float128_sqrt(xb.f128, &tstat);
env->fp_status.float_exception_flags |= tstat.float_exception_flags;
if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
if (float128_is_signaling_nan(xb.f128, &tstat)) {
float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
xt.f128 = float128_snan_to_qnan(xb.f128);
} else if (float128_is_quiet_nan(xb.f128, &tstat)) {
xt.f128 = xb.f128;
} else if (float128_is_neg(xb.f128) && !float128_is_zero(xb.f128)) {
float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1);
set_snan_bit_is_one(0, &env->fp_status);
xt.f128 = float128_default_nan(&env->fp_status);
}
}
helper_compute_fprf_float128(env, xt.f128);
putVSR(rD(opcode) + 32, &xt, env);
float_check_status(env);
}

1
target/ppc/helper.h
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@ -461,6 +461,7 @@ DEF_HELPER_2(xsrdpip, void, env, i32)
DEF_HELPER_2(xsrdpiz, void, env, i32)
DEF_HELPER_2(xsrqpi, void, env, i32)
DEF_HELPER_2(xsrqpxp, void, env, i32)
DEF_HELPER_2(xssqrtqp, void, env, i32)
DEF_HELPER_2(xsaddsp, void, env, i32)
DEF_HELPER_2(xssubsp, void, env, i32)

1
target/ppc/translate/vsx-impl.inc.c
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@ -835,6 +835,7 @@ GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xsrqpi, 0x05, 0x00, 0, PPC2_ISA300)
GEN_VSX_HELPER_2(xsrqpxp, 0x05, 0x01, 0, PPC2_ISA300)
GEN_VSX_HELPER_2(xssqrtqp, 0x04, 0x19, 0x1B, PPC2_ISA300)
GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)

1
target/ppc/translate/vsx-ops.inc.c
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@ -115,6 +115,7 @@ GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x18, opc4 | 0x1, inval)
GEN_VSX_Z23FORM_300(xsrqpi, 0x05, 0x0, 0x0, 0x0),
GEN_VSX_Z23FORM_300(xsrqpxp, 0x05, 0x1, 0x0, 0x0),
GEN_VSX_XFORM_300_EO(xssqrtqp, 0x04, 0x19, 0x1B, 0x00000001),
GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),