target/openrisc: convert to TranslatorOps
Notes: - Changed the num_insns test in insn_start to check for dc->base.num_insns > 1, since when tb_start is first called in a TB, base.num_insns is already set to 1. - Removed DISAS_NEXT from the switch in tb_stop; use DISAS_TOO_MANY instead. - Added an assert_not_reached on tb_stop for DISAS_NEXT and the default case. - Merged the two separate log_target_disas calls into the disas_log op. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Cc: Stafford Horne <shorne@gmail.com> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Emilio G. Cota
Richard Henderson
parent
1ffa4bced0
commit
a4fd3ec3c7
@ -1520,46 +1520,22 @@ static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu)
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}
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}
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void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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static void openrisc_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs)
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{
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DisasContext *dc = container_of(dcb, DisasContext, base);
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CPUOpenRISCState *env = cs->env_ptr;
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OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
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struct DisasContext ctx, *dc = &ctx;
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uint32_t pc_start;
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uint32_t next_page_start;
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int num_insns;
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int max_insns;
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int bound;
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pc_start = tb->pc;
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dc->base.tb = tb;
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dc->base.singlestep_enabled = cs->singlestep_enabled;
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dc->base.pc_next = pc_start;
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dc->base.is_jmp = DISAS_NEXT;
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dc->mem_idx = cpu_mmu_index(&cpu->env, false);
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dc->mem_idx = cpu_mmu_index(env, false);
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dc->tb_flags = dc->base.tb->flags;
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dc->delayed_branch = (dc->tb_flags & TB_FLAGS_DFLAG) != 0;
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bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4;
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dc->base.max_insns = MIN(dc->base.max_insns, bound);
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}
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next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
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num_insns = 0;
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max_insns = tb_cflags(tb) & CF_COUNT_MASK;
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if (max_insns == 0) {
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max_insns = CF_COUNT_MASK;
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}
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if (max_insns > TCG_MAX_INSNS) {
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max_insns = TCG_MAX_INSNS;
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}
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if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
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&& qemu_log_in_addr_range(pc_start)) {
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qemu_log_lock();
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qemu_log("----------------\n");
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qemu_log("IN: %s\n", lookup_symbol(pc_start));
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}
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gen_tb_start(tb);
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static void openrisc_tr_tb_start(DisasContextBase *db, CPUState *cs)
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{
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DisasContext *dc = container_of(db, DisasContext, base);
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/* Allow the TCG optimizer to see that R0 == 0,
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when it's true, which is the common case. */
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@ -1568,13 +1544,21 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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} else {
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cpu_R[0] = cpu_R0;
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}
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}
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static void openrisc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
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{
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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do {
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tcg_gen_insn_start(dc->base.pc_next, (dc->delayed_branch ? 1 : 0)
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| (num_insns ? 2 : 0));
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num_insns++;
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| (dc->base.num_insns > 1 ? 2 : 0));
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}
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static bool openrisc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
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const CPUBreakpoint *bp)
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{
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, BP_ANY))) {
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tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
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gen_exception(dc, EXCP_DEBUG);
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dc->base.is_jmp = DISAS_NORETURN;
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@ -1583,12 +1567,14 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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properly cleared -- thus we increment the PC here so that
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the logic setting tb->size below does the right thing. */
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dc->base.pc_next += 4;
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break;
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}
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return true;
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}
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static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
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{
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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OpenRISCCPU *cpu = OPENRISC_CPU(cs);
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if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
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gen_io_start();
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}
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disas_openrisc_insn(dc, cpu);
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dc->base.pc_next += 4;
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@ -1599,19 +1585,14 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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tcg_gen_mov_tl(cpu_pc, jmp_pc);
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tcg_gen_discard_tl(jmp_pc);
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dc->base.is_jmp = DISAS_UPDATE;
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break;
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return;
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}
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}
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} while (!dc->base.is_jmp
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&& !tcg_op_buf_full()
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&& !dc->base.singlestep_enabled
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&& !singlestep
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&& (dc->base.pc_next < next_page_start)
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&& num_insns < max_insns);
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}
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if (tb_cflags(tb) & CF_LAST_IO) {
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gen_io_end();
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}
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static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
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{
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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if ((dc->tb_flags & TB_FLAGS_DFLAG ? 1 : 0) != (dc->delayed_branch != 0)) {
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tcg_gen_movi_i32(cpu_dflag, dc->delayed_branch != 0);
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@ -1626,10 +1607,9 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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gen_exception(dc, EXCP_DEBUG);
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} else {
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switch (dc->base.is_jmp) {
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case DISAS_NEXT:
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case DISAS_TOO_MANY:
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gen_goto_tb(dc, 0, dc->base.pc_next);
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break;
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default:
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case DISAS_NORETURN:
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case DISAS_JUMP:
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case DISAS_TB_JUMP:
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@ -1639,20 +1619,35 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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to find the next TB */
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tcg_gen_exit_tb(0);
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break;
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default:
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g_assert_not_reached();
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}
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}
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}
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gen_tb_end(tb, num_insns);
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static void openrisc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs)
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{
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DisasContext *s = container_of(dcbase, DisasContext, base);
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tb->size = dc->base.pc_next - pc_start;
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tb->icount = num_insns;
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qemu_log("IN: %s\n", lookup_symbol(s->base.pc_first));
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log_target_disas(cs, s->base.pc_first, s->base.tb->size);
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}
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if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
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&& qemu_log_in_addr_range(pc_start)) {
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log_target_disas(cs, pc_start, tb->size);
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qemu_log("\n");
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qemu_log_unlock();
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}
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static const TranslatorOps openrisc_tr_ops = {
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.init_disas_context = openrisc_tr_init_disas_context,
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.tb_start = openrisc_tr_tb_start,
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.insn_start = openrisc_tr_insn_start,
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.breakpoint_check = openrisc_tr_breakpoint_check,
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.translate_insn = openrisc_tr_translate_insn,
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.tb_stop = openrisc_tr_tb_stop,
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.disas_log = openrisc_tr_disas_log,
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};
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void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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{
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DisasContext ctx;
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translator_loop(&openrisc_tr_ops, &ctx.base, cs, tb);
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}
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void openrisc_cpu_dump_state(CPUState *cs, FILE *f,
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