i.MX: split GPT and EPIT timer implementation
There is no common code between these 2 timer implementation. So it is better to split them. Signed-off-by: Jean-Christophe DUBOIS <jcd@tribudubois.net> Message-id: 1368990197-19694-1-git-send-email-jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Jean-Christophe DUBOIS
Peter Maydell
parent
37ab4a5668
commit
a50c0d6f72
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@ -11,7 +11,8 @@ common-obj-$(CONFIG_XILINX) += xilinx_timer.o
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common-obj-$(CONFIG_SLAVIO) += slavio_timer.o
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common-obj-$(CONFIG_ETRAXFS) += etraxfs_timer.o
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common-obj-$(CONFIG_GRLIB) += grlib_gptimer.o
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common-obj-$(CONFIG_IMX) += imx_timer.o
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common-obj-$(CONFIG_IMX) += imx_epit.o
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common-obj-$(CONFIG_IMX) += imx_gpt.o
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common-obj-$(CONFIG_LM32) += lm32_timer.o
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common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o
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@ -0,0 +1,404 @@
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/*
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* IMX EPIT Timer
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*
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* Copyright (c) 2008 OK Labs
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* Copyright (c) 2011 NICTA Pty Ltd
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* Originally written by Hans Jiang
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* Updated by Peter Chubb
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*
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* This code is licensed under GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*
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*/
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#include "hw/hw.h"
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#include "qemu/bitops.h"
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#include "qemu/timer.h"
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#include "hw/ptimer.h"
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#include "hw/sysbus.h"
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#include "hw/arm/imx.h"
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//#define DEBUG_TIMER 1
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#ifdef DEBUG_TIMER
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# define DPRINTF(fmt, args...) \
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do { printf("imx_timer: " fmt , ##args); } while (0)
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#else
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# define DPRINTF(fmt, args...) do {} while (0)
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#endif
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/*
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* Define to 1 for messages about attempts to
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* access unimplemented registers or similar.
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*/
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#define DEBUG_IMPLEMENTATION 1
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#if DEBUG_IMPLEMENTATION
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# define IPRINTF(fmt, args...) \
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do { fprintf(stderr, "imx_timer: " fmt, ##args); } while (0)
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#else
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# define IPRINTF(fmt, args...) do {} while (0)
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#endif
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/*
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* EPIT: Enhanced periodic interrupt timer
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*/
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#define CR_EN (1 << 0)
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#define CR_ENMOD (1 << 1)
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#define CR_OCIEN (1 << 2)
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#define CR_RLD (1 << 3)
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#define CR_PRESCALE_SHIFT (4)
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#define CR_PRESCALE_MASK (0xfff)
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#define CR_SWR (1 << 16)
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#define CR_IOVW (1 << 17)
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#define CR_DBGEN (1 << 18)
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#define CR_WAITEN (1 << 19)
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#define CR_DOZEN (1 << 20)
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#define CR_STOPEN (1 << 21)
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#define CR_CLKSRC_SHIFT (24)
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#define CR_CLKSRC_MASK (0x3 << CR_CLKSRC_SHIFT)
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#define TIMER_MAX 0XFFFFFFFFUL
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/*
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* Exact clock frequencies vary from board to board.
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* These are typical.
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*/
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static const IMXClk imx_timerp_clocks[] = {
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0, /* 00 disabled */
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IPG, /* 01 ipg_clk, ~532MHz */
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IPG, /* 10 ipg_clk_highfreq */
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CLK_32k, /* 11 ipg_clk_32k -- ~32kHz */
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};
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typedef struct {
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SysBusDevice busdev;
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ptimer_state *timer_reload;
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ptimer_state *timer_cmp;
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MemoryRegion iomem;
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DeviceState *ccm;
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uint32_t cr;
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uint32_t sr;
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uint32_t lr;
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uint32_t cmp;
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uint32_t cnt;
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uint32_t freq;
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qemu_irq irq;
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} IMXTimerPState;
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/*
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* Update interrupt status
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*/
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static void imx_timerp_update(IMXTimerPState *s)
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{
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if (s->sr && (s->cr & CR_OCIEN)) {
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qemu_irq_raise(s->irq);
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} else {
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qemu_irq_lower(s->irq);
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}
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}
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static void set_timerp_freq(IMXTimerPState *s)
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{
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unsigned clksrc;
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unsigned prescaler;
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uint32_t freq;
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clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, 2);
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prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, 12);
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freq = imx_clock_frequency(s->ccm, imx_timerp_clocks[clksrc]) / prescaler;
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s->freq = freq;
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DPRINTF("Setting ptimer frequency to %u\n", freq);
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if (freq) {
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ptimer_set_freq(s->timer_reload, freq);
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ptimer_set_freq(s->timer_cmp, freq);
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}
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}
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static void imx_timerp_reset(DeviceState *dev)
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{
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IMXTimerPState *s = container_of(dev, IMXTimerPState, busdev.qdev);
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/*
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* Soft reset doesn't touch some bits; hard reset clears them
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*/
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s->cr &= ~(CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN);
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s->sr = 0;
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s->lr = TIMER_MAX;
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s->cmp = 0;
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s->cnt = 0;
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/* stop both timers */
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ptimer_stop(s->timer_cmp);
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ptimer_stop(s->timer_reload);
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/* compute new frequency */
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set_timerp_freq(s);
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/* init both timers to TIMER_MAX */
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ptimer_set_limit(s->timer_cmp, TIMER_MAX, 1);
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ptimer_set_limit(s->timer_reload, TIMER_MAX, 1);
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if (s->freq && (s->cr & CR_EN)) {
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/* if the timer is still enabled, restart it */
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ptimer_run(s->timer_reload, 1);
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}
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}
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static uint32_t imx_timerp_update_counts(IMXTimerPState *s)
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{
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s->cnt = ptimer_get_count(s->timer_reload);
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return s->cnt;
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}
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static uint64_t imx_timerp_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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IMXTimerPState *s = (IMXTimerPState *)opaque;
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DPRINTF("p-read(offset=%x)", (unsigned int)(offset >> 2));
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switch (offset >> 2) {
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case 0: /* Control Register */
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DPRINTF("cr %x\n", s->cr);
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return s->cr;
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case 1: /* Status Register */
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DPRINTF("sr %x\n", s->sr);
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return s->sr;
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case 2: /* LR - ticks*/
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DPRINTF("lr %x\n", s->lr);
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return s->lr;
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case 3: /* CMP */
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DPRINTF("cmp %x\n", s->cmp);
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return s->cmp;
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case 4: /* CNT */
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imx_timerp_update_counts(s);
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DPRINTF(" cnt = %x\n", s->cnt);
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return s->cnt;
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}
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IPRINTF("imx_timerp_read: Bad offset %x\n",
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(int)offset >> 2);
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return 0;
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}
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static void imx_reload_compare_timer(IMXTimerPState *s)
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{
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if ((s->cr & CR_OCIEN) && s->cmp) {
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/* if the compare feature is on */
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uint32_t tmp = imx_timerp_update_counts(s);
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if (tmp > s->cmp) {
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/* reinit the cmp timer if required */
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ptimer_set_count(s->timer_cmp, tmp - s->cmp);
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if ((s->cr & CR_EN)) {
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/* Restart the cmp timer if required */
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ptimer_run(s->timer_cmp, 0);
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}
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}
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}
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}
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static void imx_timerp_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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IMXTimerPState *s = (IMXTimerPState *)opaque;
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DPRINTF("p-write(offset=%x, value = %x)\n", (unsigned int)offset >> 2,
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(unsigned int)value);
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switch (offset >> 2) {
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case 0: /* CR */
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s->cr = value & 0x03ffffff;
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if (s->cr & CR_SWR) {
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/* handle the reset */
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imx_timerp_reset(&s->busdev.qdev);
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} else {
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set_timerp_freq(s);
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}
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if (s->freq && (s->cr & CR_EN)) {
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if (s->cr & CR_ENMOD) {
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if (s->cr & CR_RLD) {
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ptimer_set_limit(s->timer_reload, s->lr, 1);
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} else {
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ptimer_set_limit(s->timer_reload, TIMER_MAX, 1);
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}
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}
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imx_reload_compare_timer(s);
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ptimer_run(s->timer_reload, 1);
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} else {
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/* stop both timers */
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ptimer_stop(s->timer_reload);
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ptimer_stop(s->timer_cmp);
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}
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break;
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case 1: /* SR - ACK*/
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/* writing 1 to OCIF clear the OCIF bit */
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if (value & 0x01) {
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s->sr = 0;
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imx_timerp_update(s);
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}
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break;
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case 2: /* LR - set ticks */
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s->lr = value;
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if (s->cr & CR_RLD) {
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/* Also set the limit if the LRD bit is set */
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/* If IOVW bit is set then set the timer value */
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ptimer_set_limit(s->timer_reload, s->lr, s->cr & CR_IOVW);
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} else if (s->cr & CR_IOVW) {
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/* If IOVW bit is set then set the timer value */
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ptimer_set_count(s->timer_reload, s->lr);
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}
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imx_reload_compare_timer(s);
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break;
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case 3: /* CMP */
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s->cmp = value;
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imx_reload_compare_timer(s);
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break;
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default:
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IPRINTF("imx_timerp_write: Bad offset %x\n",
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(int)offset >> 2);
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}
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}
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static void imx_timerp_reload(void *opaque)
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{
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IMXTimerPState *s = (IMXTimerPState *)opaque;
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DPRINTF("imxp reload\n");
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if (!(s->cr & CR_EN)) {
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return;
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}
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if (s->cr & CR_RLD) {
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ptimer_set_limit(s->timer_reload, s->lr, 1);
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} else {
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ptimer_set_limit(s->timer_reload, TIMER_MAX, 1);
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}
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if (s->cr & CR_OCIEN) {
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/* if compare register is 0 then we handle the interrupt here */
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if (s->cmp == 0) {
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s->sr = 1;
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imx_timerp_update(s);
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} else if (s->cmp <= s->lr) {
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/* We should launch the compare register */
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ptimer_set_count(s->timer_cmp, s->lr - s->cmp);
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ptimer_run(s->timer_cmp, 0);
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} else {
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IPRINTF("imxp reload: s->lr < s->cmp\n");
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}
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}
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}
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static void imx_timerp_cmp(void *opaque)
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{
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IMXTimerPState *s = (IMXTimerPState *)opaque;
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DPRINTF("imxp compare\n");
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ptimer_stop(s->timer_cmp);
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/* compare register is not 0 */
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if (s->cmp) {
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s->sr = 1;
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imx_timerp_update(s);
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}
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}
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void imx_timerp_create(const hwaddr addr,
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qemu_irq irq,
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DeviceState *ccm)
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{
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IMXTimerPState *pp;
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DeviceState *dev;
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dev = sysbus_create_simple("imx_timerp", addr, irq);
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pp = container_of(dev, IMXTimerPState, busdev.qdev);
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pp->ccm = ccm;
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}
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static const MemoryRegionOps imx_timerp_ops = {
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.read = imx_timerp_read,
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.write = imx_timerp_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static const VMStateDescription vmstate_imx_timerp = {
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.name = "imx-timerp",
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.version_id = 2,
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.minimum_version_id = 2,
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.minimum_version_id_old = 2,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(cr, IMXTimerPState),
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VMSTATE_UINT32(sr, IMXTimerPState),
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VMSTATE_UINT32(lr, IMXTimerPState),
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VMSTATE_UINT32(cmp, IMXTimerPState),
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VMSTATE_UINT32(cnt, IMXTimerPState),
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VMSTATE_UINT32(freq, IMXTimerPState),
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VMSTATE_PTIMER(timer_reload, IMXTimerPState),
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VMSTATE_PTIMER(timer_cmp, IMXTimerPState),
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VMSTATE_END_OF_LIST()
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}
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};
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static int imx_timerp_init(SysBusDevice *dev)
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{
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IMXTimerPState *s = FROM_SYSBUS(IMXTimerPState, dev);
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QEMUBH *bh;
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DPRINTF("imx_timerp_init\n");
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sysbus_init_irq(dev, &s->irq);
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memory_region_init_io(&s->iomem, &imx_timerp_ops,
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s, "imxp-timer",
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0x00001000);
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sysbus_init_mmio(dev, &s->iomem);
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bh = qemu_bh_new(imx_timerp_reload, s);
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s->timer_reload = ptimer_init(bh);
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bh = qemu_bh_new(imx_timerp_cmp, s);
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s->timer_cmp = ptimer_init(bh);
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return 0;
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}
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static void imx_timerp_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
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k->init = imx_timerp_init;
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dc->vmsd = &vmstate_imx_timerp;
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dc->reset = imx_timerp_reset;
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dc->desc = "i.MX periodic timer";
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}
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static const TypeInfo imx_timerp_info = {
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.name = "imx_timerp",
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(IMXTimerPState),
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.class_init = imx_timerp_class_init,
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};
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static void imx_timer_register_types(void)
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{
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type_register_static(&imx_timerp_info);
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}
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type_init(imx_timer_register_types)
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@ -1,5 +1,5 @@
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/*
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* IMX31 Timer
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* IMX GPT Timer
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*
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* Copyright (c) 2008 OK Labs
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* Copyright (c) 2011 NICTA Pty Ltd
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@ -12,6 +12,7 @@
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*/
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#include "hw/hw.h"
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#include "qemu/bitops.h"
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#include "qemu/timer.h"
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#include "hw/ptimer.h"
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#include "hw/sysbus.h"
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@ -54,7 +55,6 @@
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* (free-running timer from 0 to OCR1 or TIMER_MAX) .
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*/
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#define TIMER_MAX 0XFFFFFFFFUL
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/* Control register. Not all of these bits have any effect (yet) */
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@ -148,6 +148,7 @@ static void imx_timerg_set_freq(IMXTimerGState *s)
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freq = imx_clock_frequency(s->ccm, imx_timerg_clocks[clksrc]) / (1 + s->pr);
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DPRINTF("Setting gtimer clksrc %d to frequency %d\n", clksrc, freq);
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if (freq) {
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ptimer_set_freq(s->timer, freq);
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}
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@ -206,7 +207,7 @@ static uint64_t imx_timerg_read(void *opaque, hwaddr offset,
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{
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IMXTimerGState *s = (IMXTimerGState *)opaque;
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DPRINTF("g-read(offset=%x)", offset >> 2);
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DPRINTF("g-read(offset=%x)", (unsigned int)(offset >> 2));
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switch (offset >> 2) {
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case 0: /* Control Register */
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DPRINTF(" cr = %x\n", s->cr);
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@ -427,347 +428,6 @@ static int imx_timerg_init(SysBusDevice *dev)
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return 0;
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}
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/*
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* EPIT: Enhanced periodic interrupt timer
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*/
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#define CR_EN (1 << 0)
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#define CR_ENMOD (1 << 1)
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#define CR_OCIEN (1 << 2)
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#define CR_RLD (1 << 3)
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#define CR_PRESCALE_SHIFT (4)
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||||
#define CR_PRESCALE_MASK (0xfff)
|
||||
#define CR_SWR (1 << 16)
|
||||
#define CR_IOVW (1 << 17)
|
||||
#define CR_DBGEN (1 << 18)
|
||||
#define CR_WAITEN (1 << 19)
|
||||
#define CR_DOZEN (1 << 20)
|
||||
#define CR_STOPEN (1 << 21)
|
||||
#define CR_CLKSRC_SHIFT (24)
|
||||
#define CR_CLKSRC_MASK (0x3 << CR_CLKSRC_SHIFT)
|
||||
|
||||
|
||||
/*
|
||||
* Exact clock frequencies vary from board to board.
|
||||
* These are typical.
|
||||
*/
|
||||
static const IMXClk imx_timerp_clocks[] = {
|
||||
0, /* 00 disabled */
|
||||
IPG, /* 01 ipg_clk, ~532MHz */
|
||||
IPG, /* 10 ipg_clk_highfreq */
|
||||
CLK_32k, /* 11 ipg_clk_32k -- ~32kHz */
|
||||
};
|
||||
|
||||
typedef struct {
|
||||
SysBusDevice busdev;
|
||||
ptimer_state *timer_reload;
|
||||
ptimer_state *timer_cmp;
|
||||
MemoryRegion iomem;
|
||||
DeviceState *ccm;
|
||||
|
||||
uint32_t cr;
|
||||
uint32_t sr;
|
||||
uint32_t lr;
|
||||
uint32_t cmp;
|
||||
uint32_t cnt;
|
||||
|
||||
uint32_t freq;
|
||||
qemu_irq irq;
|
||||
} IMXTimerPState;
|
||||
|
||||
/*
|
||||
* Update interrupt status
|
||||
*/
|
||||
static void imx_timerp_update(IMXTimerPState *s)
|
||||
{
|
||||
if (s->sr && (s->cr & CR_OCIEN)) {
|
||||
qemu_irq_raise(s->irq);
|
||||
} else {
|
||||
qemu_irq_lower(s->irq);
|
||||
}
|
||||
}
|
||||
|
||||
static void set_timerp_freq(IMXTimerPState *s)
|
||||
{
|
||||
int clksrc;
|
||||
unsigned prescaler;
|
||||
uint32_t freq;
|
||||
|
||||
clksrc = (s->cr & CR_CLKSRC_MASK) >> CR_CLKSRC_SHIFT;
|
||||
prescaler = 1 + ((s->cr >> CR_PRESCALE_SHIFT) & CR_PRESCALE_MASK);
|
||||
freq = imx_clock_frequency(s->ccm, imx_timerp_clocks[clksrc]) / prescaler;
|
||||
|
||||
s->freq = freq;
|
||||
DPRINTF("Setting ptimer frequency to %u\n", freq);
|
||||
|
||||
if (freq) {
|
||||
ptimer_set_freq(s->timer_reload, freq);
|
||||
ptimer_set_freq(s->timer_cmp, freq);
|
||||
}
|
||||
}
|
||||
|
||||
static void imx_timerp_reset(DeviceState *dev)
|
||||
{
|
||||
IMXTimerPState *s = container_of(dev, IMXTimerPState, busdev.qdev);
|
||||
|
||||
/*
|
||||
* Soft reset doesn't touch some bits; hard reset clears them
|
||||
*/
|
||||
s->cr &= ~(CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN);
|
||||
s->sr = 0;
|
||||
s->lr = TIMER_MAX;
|
||||
s->cmp = 0;
|
||||
s->cnt = 0;
|
||||
/* stop both timers */
|
||||
ptimer_stop(s->timer_cmp);
|
||||
ptimer_stop(s->timer_reload);
|
||||
/* compute new frequency */
|
||||
set_timerp_freq(s);
|
||||
/* init both timers to TIMER_MAX */
|
||||
ptimer_set_limit(s->timer_cmp, TIMER_MAX, 1);
|
||||
ptimer_set_limit(s->timer_reload, TIMER_MAX, 1);
|
||||
if (s->freq && (s->cr & CR_EN)) {
|
||||
/* if the timer is still enabled, restart it */
|
||||
ptimer_run(s->timer_reload, 1);
|
||||
}
|
||||
}
|
||||
|
||||
static uint32_t imx_timerp_update_counts(IMXTimerPState *s)
|
||||
{
|
||||
s->cnt = ptimer_get_count(s->timer_reload);
|
||||
|
||||
return s->cnt;
|
||||
}
|
||||
|
||||
static uint64_t imx_timerp_read(void *opaque, hwaddr offset,
|
||||
unsigned size)
|
||||
{
|
||||
IMXTimerPState *s = (IMXTimerPState *)opaque;
|
||||
|
||||
DPRINTF("p-read(offset=%x)", offset >> 2);
|
||||
switch (offset >> 2) {
|
||||
case 0: /* Control Register */
|
||||
DPRINTF("cr %x\n", s->cr);
|
||||
return s->cr;
|
||||
|
||||
case 1: /* Status Register */
|
||||
DPRINTF("sr %x\n", s->sr);
|
||||
return s->sr;
|
||||
|
||||
case 2: /* LR - ticks*/
|
||||
DPRINTF("lr %x\n", s->lr);
|
||||
return s->lr;
|
||||
|
||||
case 3: /* CMP */
|
||||
DPRINTF("cmp %x\n", s->cmp);
|
||||
return s->cmp;
|
||||
|
||||
case 4: /* CNT */
|
||||
imx_timerp_update_counts(s);
|
||||
DPRINTF(" cnt = %x\n", s->cnt);
|
||||
return s->cnt;
|
||||
}
|
||||
|
||||
IPRINTF("imx_timerp_read: Bad offset %x\n",
|
||||
(int)offset >> 2);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void imx_reload_compare_timer(IMXTimerPState *s)
|
||||
{
|
||||
if ((s->cr & CR_OCIEN) && s->cmp) {
|
||||
/* if the compare feature is on */
|
||||
uint32_t tmp = imx_timerp_update_counts(s);
|
||||
if (tmp > s->cmp) {
|
||||
/* reinit the cmp timer if required */
|
||||
ptimer_set_count(s->timer_cmp, tmp - s->cmp);
|
||||
if ((s->cr & CR_EN)) {
|
||||
/* Restart the cmp timer if required */
|
||||
ptimer_run(s->timer_cmp, 0);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void imx_timerp_write(void *opaque, hwaddr offset,
|
||||
uint64_t value, unsigned size)
|
||||
{
|
||||
IMXTimerPState *s = (IMXTimerPState *)opaque;
|
||||
DPRINTF("p-write(offset=%x, value = %x)\n", (unsigned int)offset >> 2,
|
||||
(unsigned int)value);
|
||||
|
||||
switch (offset >> 2) {
|
||||
case 0: /* CR */
|
||||
s->cr = value & 0x03ffffff;
|
||||
if (s->cr & CR_SWR) {
|
||||
/* handle the reset */
|
||||
imx_timerp_reset(&s->busdev.qdev);
|
||||
} else {
|
||||
set_timerp_freq(s);
|
||||
}
|
||||
|
||||
if (s->freq && (s->cr & CR_EN)) {
|
||||
if (s->cr & CR_ENMOD) {
|
||||
if (s->cr & CR_RLD) {
|
||||
ptimer_set_limit(s->timer_reload, s->lr, 1);
|
||||
} else {
|
||||
ptimer_set_limit(s->timer_reload, TIMER_MAX, 1);
|
||||
}
|
||||
}
|
||||
|
||||
imx_reload_compare_timer(s);
|
||||
|
||||
ptimer_run(s->timer_reload, 1);
|
||||
} else {
|
||||
/* stop both timers */
|
||||
ptimer_stop(s->timer_reload);
|
||||
ptimer_stop(s->timer_cmp);
|
||||
}
|
||||
break;
|
||||
|
||||
case 1: /* SR - ACK*/
|
||||
/* writing 1 to OCIF clear the OCIF bit */
|
||||
if (value & 0x01) {
|
||||
s->sr = 0;
|
||||
imx_timerp_update(s);
|
||||
}
|
||||
break;
|
||||
|
||||
case 2: /* LR - set ticks */
|
||||
s->lr = value;
|
||||
|
||||
if (s->cr & CR_RLD) {
|
||||
/* Also set the limit if the LRD bit is set */
|
||||
/* If IOVW bit is set then set the timer value */
|
||||
ptimer_set_limit(s->timer_reload, s->lr, s->cr & CR_IOVW);
|
||||
} else if (s->cr & CR_IOVW) {
|
||||
/* If IOVW bit is set then set the timer value */
|
||||
ptimer_set_count(s->timer_reload, s->lr);
|
||||
}
|
||||
|
||||
imx_reload_compare_timer(s);
|
||||
|
||||
break;
|
||||
|
||||
case 3: /* CMP */
|
||||
s->cmp = value;
|
||||
|
||||
imx_reload_compare_timer(s);
|
||||
|
||||
break;
|
||||
|
||||
default:
|
||||
IPRINTF("imx_timerp_write: Bad offset %x\n",
|
||||
(int)offset >> 2);
|
||||
}
|
||||
}
|
||||
|
||||
static void imx_timerp_reload(void *opaque)
|
||||
{
|
||||
IMXTimerPState *s = (IMXTimerPState *)opaque;
|
||||
|
||||
DPRINTF("imxp reload\n");
|
||||
|
||||
if (!(s->cr & CR_EN)) {
|
||||
return;
|
||||
}
|
||||
|
||||
if (s->cr & CR_RLD) {
|
||||
ptimer_set_limit(s->timer_reload, s->lr, 1);
|
||||
} else {
|
||||
ptimer_set_limit(s->timer_reload, TIMER_MAX, 1);
|
||||
}
|
||||
|
||||
if (s->cr & CR_OCIEN) {
|
||||
/* if compare register is 0 then we handle the interrupt here */
|
||||
if (s->cmp == 0) {
|
||||
s->sr = 1;
|
||||
imx_timerp_update(s);
|
||||
} else if (s->cmp <= s->lr) {
|
||||
/* We should launch the compare register */
|
||||
ptimer_set_count(s->timer_cmp, s->lr - s->cmp);
|
||||
ptimer_run(s->timer_cmp, 0);
|
||||
} else {
|
||||
IPRINTF("imxp reload: s->lr < s->cmp\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void imx_timerp_cmp(void *opaque)
|
||||
{
|
||||
IMXTimerPState *s = (IMXTimerPState *)opaque;
|
||||
|
||||
DPRINTF("imxp compare\n");
|
||||
|
||||
ptimer_stop(s->timer_cmp);
|
||||
|
||||
/* compare register is not 0 */
|
||||
if (s->cmp) {
|
||||
s->sr = 1;
|
||||
imx_timerp_update(s);
|
||||
}
|
||||
}
|
||||
|
||||
void imx_timerp_create(const hwaddr addr,
|
||||
qemu_irq irq,
|
||||
DeviceState *ccm)
|
||||
{
|
||||
IMXTimerPState *pp;
|
||||
DeviceState *dev;
|
||||
|
||||
dev = sysbus_create_simple("imx_timerp", addr, irq);
|
||||
pp = container_of(dev, IMXTimerPState, busdev.qdev);
|
||||
pp->ccm = ccm;
|
||||
}
|
||||
|
||||
static const MemoryRegionOps imx_timerp_ops = {
|
||||
.read = imx_timerp_read,
|
||||
.write = imx_timerp_write,
|
||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
||||
};
|
||||
|
||||
static const VMStateDescription vmstate_imx_timerp = {
|
||||
.name = "imx-timerp",
|
||||
.version_id = 2,
|
||||
.minimum_version_id = 2,
|
||||
.minimum_version_id_old = 2,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_UINT32(cr, IMXTimerPState),
|
||||
VMSTATE_UINT32(sr, IMXTimerPState),
|
||||
VMSTATE_UINT32(lr, IMXTimerPState),
|
||||
VMSTATE_UINT32(cmp, IMXTimerPState),
|
||||
VMSTATE_UINT32(cnt, IMXTimerPState),
|
||||
VMSTATE_UINT32(freq, IMXTimerPState),
|
||||
VMSTATE_PTIMER(timer_reload, IMXTimerPState),
|
||||
VMSTATE_PTIMER(timer_cmp, IMXTimerPState),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
|
||||
static int imx_timerp_init(SysBusDevice *dev)
|
||||
{
|
||||
IMXTimerPState *s = FROM_SYSBUS(IMXTimerPState, dev);
|
||||
QEMUBH *bh;
|
||||
|
||||
DPRINTF("imx_timerp_init\n");
|
||||
sysbus_init_irq(dev, &s->irq);
|
||||
memory_region_init_io(&s->iomem, &imx_timerp_ops,
|
||||
s, "imxp-timer",
|
||||
0x00001000);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
|
||||
bh = qemu_bh_new(imx_timerp_reload, s);
|
||||
s->timer_reload = ptimer_init(bh);
|
||||
|
||||
bh = qemu_bh_new(imx_timerp_cmp, s);
|
||||
s->timer_cmp = ptimer_init(bh);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
void imx_timerg_create(const hwaddr addr,
|
||||
qemu_irq irq,
|
||||
DeviceState *ccm)
|
||||
|
|
@ -790,23 +450,6 @@ static void imx_timerg_class_init(ObjectClass *klass, void *data)
|
|||
dc->desc = "i.MX general timer";
|
||||
}
|
||||
|
||||
static void imx_timerp_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
|
||||
k->init = imx_timerp_init;
|
||||
dc->vmsd = &vmstate_imx_timerp;
|
||||
dc->reset = imx_timerp_reset;
|
||||
dc->desc = "i.MX periodic timer";
|
||||
}
|
||||
|
||||
static const TypeInfo imx_timerp_info = {
|
||||
.name = "imx_timerp",
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(IMXTimerPState),
|
||||
.class_init = imx_timerp_class_init,
|
||||
};
|
||||
|
||||
static const TypeInfo imx_timerg_info = {
|
||||
.name = "imx_timerg",
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
|
|
@ -816,7 +459,6 @@ static const TypeInfo imx_timerg_info = {
|
|||
|
||||
static void imx_timer_register_types(void)
|
||||
{
|
||||
type_register_static(&imx_timerp_info);
|
||||
type_register_static(&imx_timerg_info);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue