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target-arm: A64: add support for ld/st with index 

This adds support for the pre/post-index ld/st forms with immediate
offsets as well as the un-scaled immediate form (which are all
variations on the same 9-bit immediate instruction form).

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Alex Bennée 2013-12-23 23:27:29 +00:00 committed by Peter Maydell
parent 229b7a05e3
commit a5e94a9d76
1 changed files with 124 additions and 1 deletions
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125
target-arm/translate-a64.c
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@ -949,6 +949,110 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn)
}
}
/*
* C3.3.8 Load/store (immediate post-indexed)
* C3.3.9 Load/store (immediate pre-indexed)
* C3.3.12 Load/store (unscaled immediate)
*
* 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
* +----+-------+---+-----+-----+---+--------+-----+------+------+
* |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
* +----+-------+---+-----+-----+---+--------+-----+------+------+
*
* idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
* V = 0 -> non-vector
* size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
* opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
*/
static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn)
{
int rt = extract32(insn, 0, 5);
int rn = extract32(insn, 5, 5);
int imm9 = sextract32(insn, 12, 9);
int opc = extract32(insn, 22, 2);
int size = extract32(insn, 30, 2);
int idx = extract32(insn, 10, 2);
bool is_signed = false;
bool is_store = false;
bool is_extended = false;
bool is_vector = extract32(insn, 26, 1);
bool post_index;
bool writeback;
TCGv_i64 tcg_addr;
if (is_vector) {
size |= (opc & 2) << 1;
if (size > 4) {
unallocated_encoding(s);
return;
}
is_store = ((opc & 1) == 0);
} else {
if (size == 3 && opc == 2) {
/* PRFM - prefetch */
return;
}
if (opc == 3 && size > 1) {
unallocated_encoding(s);
return;
}
is_store = (opc == 0);
is_signed = opc & (1<<1);
is_extended = (size < 3) && (opc & 1);
}
switch (idx) {
case 0:
post_index = false;
writeback = false;
break;
case 1:
post_index = true;
writeback = true;
break;
case 3:
post_index = false;
writeback = true;
break;
case 2:
g_assert(false);
break;
}
if (rn == 31) {
gen_check_sp_alignment(s);
}
tcg_addr = read_cpu_reg_sp(s, rn, 1);
if (!post_index) {
tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9);
}
if (is_vector) {
if (is_store) {
do_fp_st(s, rt, tcg_addr, size);
} else {
do_fp_ld(s, rt, tcg_addr, size);
}
} else {
TCGv_i64 tcg_rt = cpu_reg(s, rt);
if (is_store) {
do_gpr_st(s, tcg_rt, tcg_addr, size);
} else {
do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, is_extended);
}
}
if (writeback) {
TCGv_i64 tcg_rn = cpu_reg_sp(s, rn);
if (post_index) {
tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9);
}
tcg_gen_mov_i64(tcg_rn, tcg_addr);
}
}
/*
* C3.3.10 Load/store (register offset)
*
@ -1116,6 +1220,25 @@ static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn)
}
}
/* Load/store register (immediate forms) */
static void disas_ldst_reg_imm(DisasContext *s, uint32_t insn)
{
switch (extract32(insn, 10, 2)) {
case 0: case 1: case 3:
/* Load/store register (unscaled immediate) */
/* Load/store immediate pre/post-indexed */
disas_ldst_reg_imm9(s, insn);
break;
case 2:
/* Load/store register unprivileged */
unsupported_encoding(s, insn);
break;
default:
unallocated_encoding(s);
break;
}
}
/* Load/store register (all forms) */
static void disas_ldst_reg(DisasContext *s, uint32_t insn)
{
@ -1124,7 +1247,7 @@ static void disas_ldst_reg(DisasContext *s, uint32_t insn)
if (extract32(insn, 21, 1) == 1 && extract32(insn, 10, 2) == 2) {
disas_ldst_reg_roffset(s, insn);
} else {
unsupported_encoding(s, insn);
disas_ldst_reg_imm(s, insn);
}
break;
case 1: