hw/net/can: interrupt cleanup
Define two functions to update the interrupt state, and call them on loadvm. This removes the need to migrate the state as part of vmstate_kvaser_pci. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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e73e09481c
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@ -264,10 +264,10 @@ static const VMStateDescription vmstate_kvaser_pci = {
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(dev, KvaserPCIState),
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/* Load this before sja_state. */
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VMSTATE_UINT32(s5920_intcsr, KvaserPCIState),
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VMSTATE_STRUCT(sja_state, KvaserPCIState, 0, vmstate_can_sja,
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CanSJA1000State),
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VMSTATE_UINT32(s5920_intcsr, KvaserPCIState),
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VMSTATE_UINT32(s5920_irqstate, KvaserPCIState),
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VMSTATE_END_OF_LIST()
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}
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};
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@ -378,6 +378,24 @@ static int frame2buff_bas(const qemu_can_frame *frame, uint8_t *buff)
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return frame->can_dlc + 2;
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}
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static void can_sja_update_pel_irq(CanSJA1000State *s)
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{
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if (s->interrupt_en & s->interrupt_pel) {
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qemu_irq_raise(s->irq);
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} else {
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qemu_irq_lower(s->irq);
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}
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}
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static void can_sja_update_bas_irq(CanSJA1000State *s)
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{
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if ((s->control >> 1) & s->interrupt_bas) {
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qemu_irq_raise(s->irq);
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} else {
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qemu_irq_lower(s->irq);
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}
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}
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void can_sja_mem_write(CanSJA1000State *s, hwaddr addr, uint64_t val,
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unsigned size)
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{
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@ -457,9 +475,7 @@ void can_sja_mem_write(CanSJA1000State *s, hwaddr addr, uint64_t val,
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/* Clear transmit status. */
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s->status_pel &= ~(1 << 5);
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s->interrupt_pel |= 0x02;
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if (s->interrupt_en & 0x02) {
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qemu_irq_raise(s->irq);
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}
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can_sja_update_pel_irq(s);
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}
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if (0x04 & val) { /* Release Receive Buffer */
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if (s->rxmsg_cnt <= 0) {
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@ -488,19 +504,13 @@ void can_sja_mem_write(CanSJA1000State *s, hwaddr addr, uint64_t val,
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if (s->rxmsg_cnt == 0) {
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s->status_pel &= ~(1 << 0);
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s->interrupt_pel &= ~(1 << 0);
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}
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if ((s->interrupt_en & 0x01) && (s->interrupt_pel == 0)) {
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/* no other interrupts. */
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qemu_irq_lower(s->irq);
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can_sja_update_pel_irq(s);
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}
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}
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if (0x08 & val) { /* Clear data overrun */
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s->status_pel &= ~(1 << 1);
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s->interrupt_pel &= ~(1 << 3);
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if ((s->interrupt_en & 0x80) && (s->interrupt_pel == 0)) {
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/* no other interrupts. */
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qemu_irq_lower(s->irq);
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}
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can_sja_update_pel_irq(s);
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}
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break;
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case SJA_SR: /* Status register */
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@ -568,9 +578,7 @@ void can_sja_mem_write(CanSJA1000State *s, hwaddr addr, uint64_t val,
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/* Clear transmit status. */
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s->status_bas &= ~(1 << 5);
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s->interrupt_bas |= 0x02;
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if (s->control & 0x04) {
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qemu_irq_raise(s->irq);
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}
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can_sja_update_bas_irq(s);
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}
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if (0x04 & val) { /* Release Receive Buffer */
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if (s->rxmsg_cnt <= 0) {
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@ -593,19 +601,13 @@ void can_sja_mem_write(CanSJA1000State *s, hwaddr addr, uint64_t val,
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if (s->rxmsg_cnt == 0) {
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s->status_bas &= ~(1 << 0);
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s->interrupt_bas &= ~(1 << 0);
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}
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if ((s->control & 0x02) && (s->interrupt_bas == 0)) {
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/* no other interrupts. */
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qemu_irq_lower(s->irq);
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can_sja_update_bas_irq(s);
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}
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}
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if (0x08 & val) { /* Clear data overrun */
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s->status_bas &= ~(1 << 1);
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s->interrupt_bas &= ~(1 << 3);
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if ((s->control & 0x10) && (s->interrupt_bas == 0)) {
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/* no other interrupts. */
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qemu_irq_lower(s->irq);
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}
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can_sja_update_bas_irq(s);
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}
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break;
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case 4:
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@ -654,9 +656,8 @@ uint64_t can_sja_mem_read(CanSJA1000State *s, hwaddr addr, unsigned size)
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s->interrupt_pel = 0;
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if (s->rxmsg_cnt) {
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s->interrupt_pel |= (1 << 0); /* Receive interrupt. */
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break;
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}
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qemu_irq_lower(s->irq);
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can_sja_update_pel_irq(s);
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break;
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case SJA_IER: /* Interrupt enable register, addr 4 */
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temp = s->interrupt_en;
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@ -704,9 +705,8 @@ uint64_t can_sja_mem_read(CanSJA1000State *s, hwaddr addr, unsigned size)
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s->interrupt_bas = 0;
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if (s->rxmsg_cnt) {
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s->interrupt_bas |= (1 << 0); /* Receive interrupt. */
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break;
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}
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qemu_irq_lower(s->irq);
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can_sja_update_bas_irq(s);
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break;
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case 4:
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temp = s->code;
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@ -789,13 +789,11 @@ ssize_t can_sja_receive(CanBusClientState *client, const qemu_can_frame *frames,
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if (s->rx_cnt + ret > SJA_RCV_BUF_LEN) { /* Data overrun. */
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s->status_pel |= (1 << 1); /* Overrun status */
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s->interrupt_pel |= (1 << 3);
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if (s->interrupt_en & (1 << 3)) { /* Overrun interrupt enable */
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qemu_irq_raise(s->irq);
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}
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s->status_pel &= ~(1 << 4);
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if (DEBUG_FILTER) {
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qemu_log("[cansja]: receive FIFO overrun\n");
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}
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can_sja_update_pel_irq(s);
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return ret;
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}
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s->rx_cnt += ret;
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@ -813,9 +811,7 @@ ssize_t can_sja_receive(CanBusClientState *client, const qemu_can_frame *frames,
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s->interrupt_pel |= 0x01;
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s->status_pel &= ~(1 << 4);
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s->status_pel |= (1 << 0);
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if (s->interrupt_en & 0x01) { /* Receive Interrupt enable. */
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qemu_irq_raise(s->irq);
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}
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can_sja_update_pel_irq(s);
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} else { /* BasicCAN mode */
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/* the CAN controller is receiving a message */
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@ -834,9 +830,7 @@ ssize_t can_sja_receive(CanBusClientState *client, const qemu_can_frame *frames,
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s->status_bas |= (1 << 1); /* Overrun status */
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s->status_bas &= ~(1 << 4);
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s->interrupt_bas |= (1 << 3);
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if (s->control & (1 << 4)) { /* Overrun interrupt enable */
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qemu_irq_raise(s->irq);
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}
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can_sja_update_bas_irq(s);
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if (DEBUG_FILTER) {
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qemu_log("[cansja]: receive FIFO overrun\n");
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}
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@ -856,10 +850,8 @@ ssize_t can_sja_receive(CanBusClientState *client, const qemu_can_frame *frames,
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s->status_bas |= 0x01; /* Set the Receive Buffer Status. DS-p15 */
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s->status_bas &= ~(1 << 4);
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s->interrupt_bas |= 0x01;
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if (s->control & 0x02) { /* Receive Interrupt enable. */
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qemu_irq_raise(s->irq);
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}
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s->interrupt_bas |= (1 << 0);
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can_sja_update_bas_irq(s);
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}
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return 1;
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}
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@ -909,12 +901,24 @@ const VMStateDescription vmstate_qemu_can_filter = {
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}
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};
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static int can_sja_post_load(void *opaque, int version_id)
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{
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CanSJA1000State *s = opaque;
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if (s->clock & 0x80) { /* PeliCAN Mode */
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can_sja_update_pel_irq(s);
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} else {
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can_sja_update_bas_irq(s);
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}
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return 0;
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}
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/* VMState is needed for live migration of QEMU images */
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const VMStateDescription vmstate_can_sja = {
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.name = "can_sja",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.post_load = can_sja_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8(mode, CanSJA1000State),
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