target/arm: Use isar_feature_aa32_simd_r32 more places
Many uses of ARM_FEATURE_VFP3 are testing for the number of simd registers implemented. Use the proper test vs MVFR0.SIMDReg. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200214181547.21408-4-richard.henderson@linaro.org [PMM: fix typo in commit message] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -1009,11 +1009,10 @@ static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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if (flags & CPU_DUMP_FPU) {
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if (flags & CPU_DUMP_FPU) {
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int numvfpregs = 0;
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int numvfpregs = 0;
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if (arm_feature(env, ARM_FEATURE_VFP)) {
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if (cpu_isar_feature(aa32_simd_r32, cpu)) {
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numvfpregs += 16;
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numvfpregs = 32;
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}
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} else if (arm_feature(env, ARM_FEATURE_VFP)) {
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if (arm_feature(env, ARM_FEATURE_VFP3)) {
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numvfpregs = 16;
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numvfpregs += 16;
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}
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}
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for (i = 0; i < numvfpregs; i++) {
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for (i = 0; i < numvfpregs; i++) {
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uint64_t v = *aa32_vfp_dreg(env, i);
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uint64_t v = *aa32_vfp_dreg(env, i);
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@ -50,10 +50,10 @@ static void switch_mode(CPUARMState *env, int mode);
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static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
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static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
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{
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{
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int nregs;
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ARMCPU *cpu = env_archcpu(env);
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int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;
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/* VFP data registers are always little-endian. */
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/* VFP data registers are always little-endian. */
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nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
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if (reg < nregs) {
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if (reg < nregs) {
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stq_le_p(buf, *aa32_vfp_dreg(env, reg));
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stq_le_p(buf, *aa32_vfp_dreg(env, reg));
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return 8;
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return 8;
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@ -78,9 +78,9 @@ static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
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static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
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static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
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{
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{
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int nregs;
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ARMCPU *cpu = env_archcpu(env);
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int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;
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nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
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if (reg < nregs) {
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if (reg < nregs) {
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*aa32_vfp_dreg(env, reg) = ldq_le_p(buf);
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*aa32_vfp_dreg(env, reg) = ldq_le_p(buf);
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return 8;
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return 8;
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@ -906,8 +906,7 @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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/* VFPv3 and upwards with NEON implement 32 double precision
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/* VFPv3 and upwards with NEON implement 32 double precision
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* registers (D0-D31).
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* registers (D0-D31).
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*/
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*/
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if (!arm_feature(env, ARM_FEATURE_NEON) ||
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if (!cpu_isar_feature(aa32_simd_r32, env_archcpu(env))) {
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!arm_feature(env, ARM_FEATURE_VFP3)) {
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/* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
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/* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
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value |= (1 << 30);
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value |= (1 << 30);
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}
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}
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@ -7812,7 +7811,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
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} else if (arm_feature(env, ARM_FEATURE_NEON)) {
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} else if (arm_feature(env, ARM_FEATURE_NEON)) {
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gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
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gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
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51, "arm-neon.xml", 0);
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51, "arm-neon.xml", 0);
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} else if (arm_feature(env, ARM_FEATURE_VFP3)) {
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} else if (cpu_isar_feature(aa32_simd_r32, cpu)) {
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gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
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gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
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35, "arm-vfp3.xml", 0);
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35, "arm-vfp3.xml", 0);
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} else if (arm_feature(env, ARM_FEATURE_VFP)) {
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} else if (arm_feature(env, ARM_FEATURE_VFP)) {
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@ -2612,7 +2612,7 @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn)
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#define VFP_SREG(insn, bigbit, smallbit) \
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#define VFP_SREG(insn, bigbit, smallbit) \
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((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
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((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
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#define VFP_DREG(reg, insn, bigbit, smallbit) do { \
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#define VFP_DREG(reg, insn, bigbit, smallbit) do { \
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if (arm_dc_feature(s, ARM_FEATURE_VFP3)) { \
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if (dc_isar_feature(aa32_simd_r32, s)) { \
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reg = (((insn) >> (bigbit)) & 0x0f) \
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reg = (((insn) >> (bigbit)) & 0x0f) \
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| (((insn) >> ((smallbit) - 4)) & 0x10); \
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| (((insn) >> ((smallbit) - 4)) & 0x10); \
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} else { \
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} else { \
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