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target/arm: Use isar_feature_aa32_simd_r32 more places 

Many uses of ARM_FEATURE_VFP3 are testing for the number of simd
registers implemented.  Use the proper test vs MVFR0.SIMDReg.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200214181547.21408-4-richard.henderson@linaro.org
[PMM: fix typo in commit message]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2020-02-14 10:15:31 -08:00 committed by Peter Maydell
parent 0e13ba7889
commit a6627f5fc6
3 changed files with 11 additions and 13 deletions
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9
target/arm/cpu.c
View File

@ -1009,11 +1009,10 @@ static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
if (flags & CPU_DUMP_FPU) { if (flags & CPU_DUMP_FPU) {
int numvfpregs = 0; int numvfpregs = 0;
if (arm_feature(env, ARM_FEATURE_VFP)) { if (cpu_isar_feature(aa32_simd_r32, cpu)) {
numvfpregs += 16; numvfpregs = 32;
} } else if (arm_feature(env, ARM_FEATURE_VFP)) {
if (arm_feature(env, ARM_FEATURE_VFP3)) { numvfpregs = 16;
numvfpregs += 16;
} }
for (i = 0; i < numvfpregs; i++) { for (i = 0; i < numvfpregs; i++) {
uint64_t v = *aa32_vfp_dreg(env, i); uint64_t v = *aa32_vfp_dreg(env, i);

13
target/arm/helper.c
View File

@ -50,10 +50,10 @@ static void switch_mode(CPUARMState *env, int mode);
static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
{ {
int nregs; ARMCPU *cpu = env_archcpu(env);
int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;
/* VFP data registers are always little-endian. */ /* VFP data registers are always little-endian. */
nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
if (reg < nregs) { if (reg < nregs) {
stq_le_p(buf, *aa32_vfp_dreg(env, reg)); stq_le_p(buf, *aa32_vfp_dreg(env, reg));
return 8; return 8;
@ -78,9 +78,9 @@ static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
{ {
int nregs; ARMCPU *cpu = env_archcpu(env);
int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;
nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
if (reg < nregs) { if (reg < nregs) {
*aa32_vfp_dreg(env, reg) = ldq_le_p(buf); *aa32_vfp_dreg(env, reg) = ldq_le_p(buf);
return 8; return 8;
@ -906,8 +906,7 @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
/* VFPv3 and upwards with NEON implement 32 double precision /* VFPv3 and upwards with NEON implement 32 double precision
* registers (D0-D31). * registers (D0-D31).
*/ */
if (!arm_feature(env, ARM_FEATURE_NEON) || if (!cpu_isar_feature(aa32_simd_r32, env_archcpu(env))) {
!arm_feature(env, ARM_FEATURE_VFP3)) {
/* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
value |= (1 << 30); value |= (1 << 30);
} }
@ -7812,7 +7811,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
} else if (arm_feature(env, ARM_FEATURE_NEON)) { } else if (arm_feature(env, ARM_FEATURE_NEON)) {
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
51, "arm-neon.xml", 0); 51, "arm-neon.xml", 0);
} else if (arm_feature(env, ARM_FEATURE_VFP3)) { } else if (cpu_isar_feature(aa32_simd_r32, cpu)) {
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
35, "arm-vfp3.xml", 0); 35, "arm-vfp3.xml", 0);
} else if (arm_feature(env, ARM_FEATURE_VFP)) { } else if (arm_feature(env, ARM_FEATURE_VFP)) {

2
target/arm/translate.c
View File

@ -2612,7 +2612,7 @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn)
#define VFP_SREG(insn, bigbit, smallbit) \ #define VFP_SREG(insn, bigbit, smallbit) \
((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1)) ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
#define VFP_DREG(reg, insn, bigbit, smallbit) do { \ #define VFP_DREG(reg, insn, bigbit, smallbit) do { \
if (arm_dc_feature(s, ARM_FEATURE_VFP3)) { \ if (dc_isar_feature(aa32_simd_r32, s)) { \
reg = (((insn) >> (bigbit)) & 0x0f) \ reg = (((insn) >> (bigbit)) & 0x0f) \
| (((insn) >> ((smallbit) - 4)) & 0x10); \ | (((insn) >> ((smallbit) - 4)) & 0x10); \
} else { \ } else { \