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target/loongarch: Add exception subcode 

We need subcodes to distinguish the same excode cs->exception_indexs,
such as EXCCODE_ADEF/EXCCODE_ADEM.

Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20221101073210.3934280-1-gaosong@loongson.cn>
This commit is contained in:
Song Gao 2022-11-01 11:17:15 +08:00
parent 3dfbb6dee5
commit a6b129c810
No known key found for this signature in database
GPG Key ID: 40A2FFF239263EDF
2 changed files with 36 additions and 29 deletions
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7
target/loongarch/cpu.c
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@ -220,7 +220,10 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA,
PC, (env->pc >> 2)); PC, (env->pc >> 2));
} else { } else {
env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE, cause); env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE,
EXCODE_MCODE(cause));
env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ESUBCODE,
EXCODE_SUBCODE(cause));
env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV, env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV,
FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV)); FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV));
env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE, env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE,
@ -257,7 +260,7 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
env->pc = env->CSR_TLBRENTRY; env->pc = env->CSR_TLBRENTRY;
} else { } else {
env->pc = env->CSR_EENTRY; env->pc = env->CSR_EENTRY;
env->pc += cause * vec_size; env->pc += EXCODE_MCODE(cause) * vec_size;
} }
qemu_log_mask(CPU_LOG_INT, qemu_log_mask(CPU_LOG_INT,
"%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx

58
target/loongarch/cpu.h
View File

@ -75,33 +75,37 @@ FIELD(FCSR0, CAUSE, 24, 5)
#define FP_DIV0 8 #define FP_DIV0 8
#define FP_INVALID 16 #define FP_INVALID 16
#define EXCCODE_EXTERNAL_INT 64 /* plus external interrupt number */ #define EXCODE(code, subcode) ( ((subcode) << 6) | (code) )
#define EXCCODE_INT 0 #define EXCODE_MCODE(code) ( (code) & 0x3f )
#define EXCCODE_PIL 1 #define EXCODE_SUBCODE(code) ( (code) >> 6 )
#define EXCCODE_PIS 2
#define EXCCODE_PIF 3 #define EXCCODE_EXTERNAL_INT 64 /* plus external interrupt number */
#define EXCCODE_PME 4 #define EXCCODE_INT EXCODE(0, 0)
#define EXCCODE_PNR 5 #define EXCCODE_PIL EXCODE(1, 0)
#define EXCCODE_PNX 6 #define EXCCODE_PIS EXCODE(2, 0)
#define EXCCODE_PPI 7 #define EXCCODE_PIF EXCODE(3, 0)
#define EXCCODE_ADEF 8 /* Different exception subcode */ #define EXCCODE_PME EXCODE(4, 0)
#define EXCCODE_ADEM 8 #define EXCCODE_PNR EXCODE(5, 0)
#define EXCCODE_ALE 9 #define EXCCODE_PNX EXCODE(6, 0)
#define EXCCODE_BCE 10 #define EXCCODE_PPI EXCODE(7, 0)
#define EXCCODE_SYS 11 #define EXCCODE_ADEF EXCODE(8, 0) /* Different exception subcode */
#define EXCCODE_BRK 12 #define EXCCODE_ADEM EXCODE(8, 1)
#define EXCCODE_INE 13 #define EXCCODE_ALE EXCODE(9, 0)
#define EXCCODE_IPE 14 #define EXCCODE_BCE EXCODE(10, 0)
#define EXCCODE_FPD 15 #define EXCCODE_SYS EXCODE(11, 0)
#define EXCCODE_SXD 16 #define EXCCODE_BRK EXCODE(12, 0)
#define EXCCODE_ASXD 17 #define EXCCODE_INE EXCODE(13, 0)
#define EXCCODE_FPE 18 /* Different exception subcode */ #define EXCCODE_IPE EXCODE(14, 0)
#define EXCCODE_VFPE 18 #define EXCCODE_FPD EXCODE(15, 0)
#define EXCCODE_WPEF 19 /* Different exception subcode */ #define EXCCODE_SXD EXCODE(16, 0)
#define EXCCODE_WPEM 19 #define EXCCODE_ASXD EXCODE(17, 0)
#define EXCCODE_BTD 20 #define EXCCODE_FPE EXCODE(18, 0) /* Different exception subcode */
#define EXCCODE_BTE 21 #define EXCCODE_VFPE EXCODE(18, 1)
#define EXCCODE_DBP 26 /* Reserved subcode used for debug */ #define EXCCODE_WPEF EXCODE(19, 0) /* Different exception subcode */
#define EXCCODE_WPEM EXCODE(19, 1)
#define EXCCODE_BTD EXCODE(20, 0)
#define EXCCODE_BTE EXCODE(21, 0)
#define EXCCODE_DBP EXCODE(26, 0) /* Reserved subcode used for debug */
/* cpucfg[0] bits */ /* cpucfg[0] bits */
FIELD(CPUCFG0, PRID, 0, 32) FIELD(CPUCFG0, PRID, 0, 32)