ppc/pegasos2: Use Virtual Open Firmware as firmware replacement
The pegasos2 board comes with an Open Firmware compliant ROM based on SmartFirmware but it has some changes that are not open source therefore the ROM binary cannot be included in QEMU. Guests running on the board however depend on services provided by the firmware. The Virtual Open Firmware recently added to QEMU implements a minimal set of these services to allow some guests to boot without the original firmware. This patch adds VOF as the default firmware for pegasos2 which allows booting Linux and MorphOS via -kernel option while a ROM image can still be used with -bios for guests that don't run with VOF. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <1d6ed6f290c5c1f0b5a1e1c51cf1151452d70d9a.1624811233.git.balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
BALATON Zoltan
David Gibson
parent
17fd09c021
commit
a6c9808a68
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@ -76,6 +76,7 @@ config PEGASOS2
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select VT82C686
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select IDE_VIA
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select SMBUS_EEPROM
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select VOF
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# This should come with VT82C686
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select ACPI_X86
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@ -34,13 +34,33 @@
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#include "trace.h"
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#include "qemu/datadir.h"
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#include "sysemu/device_tree.h"
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#include "hw/ppc/vof.h"
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#define PROM_FILENAME "pegasos2.rom"
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#include <libfdt.h>
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#define PROM_FILENAME "vof.bin"
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#define PROM_ADDR 0xfff00000
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#define PROM_SIZE 0x80000
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#define KVMPPC_HCALL_BASE 0xf000
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#define KVMPPC_H_VOF_CLIENT (KVMPPC_HCALL_BASE + 0x5)
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#define H_SUCCESS 0
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#define H_PRIVILEGE -3 /* Caller not privileged */
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#define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */
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#define BUS_FREQ_HZ 133333333
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#define PCI0_MEM_BASE 0xc0000000
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#define PCI0_MEM_SIZE 0x20000000
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#define PCI0_IO_BASE 0xf8000000
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#define PCI0_IO_SIZE 0x10000
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#define PCI1_MEM_BASE 0x80000000
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#define PCI1_MEM_SIZE 0x40000000
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#define PCI1_IO_BASE 0xfe000000
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#define PCI1_IO_SIZE 0x10000
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#define TYPE_PEGASOS2_MACHINE MACHINE_TYPE_NAME("pegasos2")
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OBJECT_DECLARE_TYPE(Pegasos2MachineState, MachineClass, PEGASOS2_MACHINE)
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@ -48,14 +68,26 @@ struct Pegasos2MachineState {
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MachineState parent_obj;
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PowerPCCPU *cpu;
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DeviceState *mv;
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Vof *vof;
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void *fdt_blob;
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uint64_t kernel_addr;
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uint64_t kernel_entry;
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uint64_t kernel_size;
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};
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static void *build_fdt(MachineState *machine, int *fdt_size);
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static void pegasos2_cpu_reset(void *opaque)
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{
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PowerPCCPU *cpu = opaque;
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Pegasos2MachineState *pm = PEGASOS2_MACHINE(current_machine);
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cpu_reset(CPU(cpu));
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cpu->env.spr[SPR_HID1] = 7ULL << 28;
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if (pm->vof) {
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cpu->env.gpr[1] = 2 * VOF_STACK_SIZE - 0x20;
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cpu->env.nip = 0x100;
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}
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}
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static void pegasos2_init(MachineState *machine)
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@ -92,18 +124,24 @@ static void pegasos2_init(MachineState *machine)
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error_report("Could not find firmware '%s'", fwname);
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exit(1);
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}
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if (!machine->firmware && !pm->vof) {
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pm->vof = g_malloc0(sizeof(*pm->vof));
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}
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memory_region_init_rom(rom, NULL, "pegasos2.rom", PROM_SIZE, &error_fatal);
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memory_region_add_subregion(get_system_memory(), PROM_ADDR, rom);
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sz = load_elf(filename, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 1,
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PPC_ELF_MACHINE, 0, 0);
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if (sz <= 0) {
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sz = load_image_targphys(filename, PROM_ADDR, PROM_SIZE);
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sz = load_image_targphys(filename, pm->vof ? 0 : PROM_ADDR, PROM_SIZE);
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}
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if (sz <= 0 || sz > PROM_SIZE) {
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error_report("Could not load firmware '%s'", filename);
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exit(1);
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}
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g_free(filename);
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if (pm->vof) {
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pm->vof->fw_size = sz;
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}
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/* Marvell Discovery II system controller */
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pm->mv = DEVICE(sysbus_create_simple(TYPE_MV64361, -1,
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@ -137,20 +175,185 @@ static void pegasos2_init(MachineState *machine)
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/* other PC hardware */
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pci_vga_init(pci_bus);
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if (machine->kernel_filename) {
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sz = load_elf(machine->kernel_filename, NULL, NULL, NULL,
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&pm->kernel_entry, &pm->kernel_addr, NULL, NULL, 1,
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PPC_ELF_MACHINE, 0, 0);
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if (sz <= 0) {
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error_report("Could not load kernel '%s'",
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machine->kernel_filename);
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exit(1);
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}
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pm->kernel_size = sz;
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if (!pm->vof) {
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warn_report("Option -kernel may be ineffective with -bios.");
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}
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}
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if (machine->kernel_cmdline && !pm->vof) {
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warn_report("Option -append may be ineffective with -bios.");
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}
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}
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static void pegasos2_pci_config_write(AddressSpace *as, int bus, uint32_t addr,
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uint32_t len, uint32_t val)
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{
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hwaddr pcicfg = (bus ? 0xf1000c78 : 0xf1000cf8);
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stl_le_phys(as, pcicfg, addr | BIT(31));
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switch (len) {
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case 4:
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stl_le_phys(as, pcicfg + 4, val);
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break;
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case 2:
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stw_le_phys(as, pcicfg + 4, val);
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break;
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case 1:
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stb_phys(as, pcicfg + 4, val);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid length\n", __func__);
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break;
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}
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}
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static void pegasos2_machine_reset(MachineState *machine)
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{
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Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine);
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AddressSpace *as = CPU(pm->cpu)->as;
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void *fdt;
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uint64_t d[2];
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int sz;
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qemu_devices_reset();
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if (!pm->vof) {
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return; /* Firmware should set up machine so nothing to do */
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}
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/* Otherwise, set up devices that board firmware would normally do */
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stl_le_phys(as, 0xf1000000, 0x28020ff);
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stl_le_phys(as, 0xf1000278, 0xa31fc);
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stl_le_phys(as, 0xf100f300, 0x11ff0400);
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stl_le_phys(as, 0xf100f10c, 0x80000000);
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stl_le_phys(as, 0xf100001c, 0x8000000);
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pegasos2_pci_config_write(as, 0, PCI_COMMAND, 2, PCI_COMMAND_IO |
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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pegasos2_pci_config_write(as, 1, PCI_COMMAND, 2, PCI_COMMAND_IO |
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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pegasos2_pci_config_write(as, 1, (PCI_DEVFN(12, 0) << 8) |
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PCI_INTERRUPT_LINE, 2, 0x9);
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pegasos2_pci_config_write(as, 1, (PCI_DEVFN(12, 0) << 8) |
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0x50, 1, 0x2);
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pegasos2_pci_config_write(as, 1, (PCI_DEVFN(12, 1) << 8) |
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PCI_INTERRUPT_LINE, 2, 0x109);
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pegasos2_pci_config_write(as, 1, (PCI_DEVFN(12, 1) << 8) |
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PCI_CLASS_PROG, 1, 0xf);
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pegasos2_pci_config_write(as, 1, (PCI_DEVFN(12, 1) << 8) |
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0x40, 1, 0xb);
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pegasos2_pci_config_write(as, 1, (PCI_DEVFN(12, 1) << 8) |
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0x50, 4, 0x17171717);
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pegasos2_pci_config_write(as, 1, (PCI_DEVFN(12, 1) << 8) |
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PCI_COMMAND, 2, 0x87);
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pegasos2_pci_config_write(as, 1, (PCI_DEVFN(12, 2) << 8) |
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PCI_INTERRUPT_LINE, 2, 0x409);
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pegasos2_pci_config_write(as, 1, (PCI_DEVFN(12, 3) << 8) |
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PCI_INTERRUPT_LINE, 2, 0x409);
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pegasos2_pci_config_write(as, 1, (PCI_DEVFN(12, 4) << 8) |
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PCI_INTERRUPT_LINE, 2, 0x9);
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pegasos2_pci_config_write(as, 1, (PCI_DEVFN(12, 4) << 8) |
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0x48, 4, 0xf00);
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pegasos2_pci_config_write(as, 1, (PCI_DEVFN(12, 4) << 8) |
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0x40, 4, 0x558020);
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pegasos2_pci_config_write(as, 1, (PCI_DEVFN(12, 4) << 8) |
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0x90, 4, 0xd00);
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pegasos2_pci_config_write(as, 1, (PCI_DEVFN(12, 5) << 8) |
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PCI_INTERRUPT_LINE, 2, 0x309);
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pegasos2_pci_config_write(as, 1, (PCI_DEVFN(12, 6) << 8) |
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PCI_INTERRUPT_LINE, 2, 0x309);
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/* Device tree and VOF set up */
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vof_init(pm->vof, machine->ram_size, &error_fatal);
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if (vof_claim(pm->vof, 0, VOF_STACK_SIZE, VOF_STACK_SIZE) == -1) {
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error_report("Memory allocation for stack failed");
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exit(1);
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}
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if (pm->kernel_size &&
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vof_claim(pm->vof, pm->kernel_addr, pm->kernel_size, 0) == -1) {
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error_report("Memory for kernel is in use");
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exit(1);
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}
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fdt = build_fdt(machine, &sz);
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/* FIXME: VOF assumes entry is same as load address */
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d[0] = cpu_to_be64(pm->kernel_entry);
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d[1] = cpu_to_be64(pm->kernel_size - (pm->kernel_entry - pm->kernel_addr));
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qemu_fdt_setprop(fdt, "/chosen", "qemu,boot-kernel", d, sizeof(d));
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qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
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g_free(pm->fdt_blob);
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pm->fdt_blob = fdt;
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vof_build_dt(fdt, pm->vof);
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vof_client_open_store(fdt, pm->vof, "/chosen", "stdout", "/failsafe");
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pm->cpu->vhyp = PPC_VIRTUAL_HYPERVISOR(machine);
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}
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static void pegasos2_hypercall(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu)
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{
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Pegasos2MachineState *pm = PEGASOS2_MACHINE(vhyp);
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CPUPPCState *env = &cpu->env;
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/* The TCG path should also be holding the BQL at this point */
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g_assert(qemu_mutex_iothread_locked());
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if (msr_pr) {
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qemu_log_mask(LOG_GUEST_ERROR, "Hypercall made with MSR[PR]=1\n");
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env->gpr[3] = H_PRIVILEGE;
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} else if (env->gpr[3] == KVMPPC_H_VOF_CLIENT) {
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int ret = vof_client_call(MACHINE(pm), pm->vof, pm->fdt_blob,
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env->gpr[4]);
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env->gpr[3] = (ret ? H_PARAMETER : H_SUCCESS);
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} else {
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qemu_log_mask(LOG_GUEST_ERROR, "Unsupported hypercall " TARGET_FMT_lx
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"\n", env->gpr[3]);
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env->gpr[3] = -1;
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}
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}
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static void vhyp_nop(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu)
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{
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}
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static target_ulong vhyp_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp)
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{
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return POWERPC_CPU(current_cpu)->env.spr[SPR_SDR1];
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}
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static void pegasos2_machine_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
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mc->desc = "Genesi/bPlan Pegasos II";
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mc->init = pegasos2_init;
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mc->reset = pegasos2_machine_reset;
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mc->block_default_type = IF_IDE;
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mc->default_boot_order = "cd";
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mc->default_display = "std";
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mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7400_v2.9");
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mc->default_ram_id = "pegasos2.ram";
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mc->default_ram_size = 512 * MiB;
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vhc->hypercall = pegasos2_hypercall;
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vhc->cpu_exec_enter = vhyp_nop;
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vhc->cpu_exec_exit = vhyp_nop;
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vhc->encode_hpt_for_kvm_pr = vhyp_encode_hpt_for_kvm_pr;
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}
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static const TypeInfo pegasos2_machine_info = {
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@ -158,6 +361,10 @@ static const TypeInfo pegasos2_machine_info = {
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.parent = TYPE_MACHINE,
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.class_init = pegasos2_machine_class_init,
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.instance_size = sizeof(Pegasos2MachineState),
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.interfaces = (InterfaceInfo[]) {
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{ TYPE_PPC_VIRTUAL_HYPERVISOR },
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{ }
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},
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};
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static void pegasos2_machine_register_types(void)
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@ -166,3 +373,394 @@ static void pegasos2_machine_register_types(void)
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}
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type_init(pegasos2_machine_register_types)
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/* FDT creation for passing to firmware */
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typedef struct {
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void *fdt;
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const char *path;
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} FDTInfo;
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/* We do everything in reverse order so it comes out right in the tree */
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static void dt_ide(PCIBus *bus, PCIDevice *d, FDTInfo *fi)
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{
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qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "spi");
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}
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static void dt_usb(PCIBus *bus, PCIDevice *d, FDTInfo *fi)
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{
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qemu_fdt_setprop_cell(fi->fdt, fi->path, "#size-cells", 0);
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qemu_fdt_setprop_cell(fi->fdt, fi->path, "#address-cells", 1);
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qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "usb");
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}
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static void dt_isa(PCIBus *bus, PCIDevice *d, FDTInfo *fi)
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{
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GString *name = g_string_sized_new(64);
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uint32_t cells[3];
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qemu_fdt_setprop_cell(fi->fdt, fi->path, "#size-cells", 1);
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qemu_fdt_setprop_cell(fi->fdt, fi->path, "#address-cells", 2);
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qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "isa");
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qemu_fdt_setprop_string(fi->fdt, fi->path, "name", "isa");
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/* addional devices */
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g_string_printf(name, "%s/lpt@i3bc", fi->path);
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qemu_fdt_add_subnode(fi->fdt, name->str);
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qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
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cells[0] = cpu_to_be32(7);
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cells[1] = 0;
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qemu_fdt_setprop(fi->fdt, name->str, "interrupts",
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cells, 2 * sizeof(cells[0]));
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cells[0] = cpu_to_be32(1);
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cells[1] = cpu_to_be32(0x3bc);
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cells[2] = cpu_to_be32(8);
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qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
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qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "lpt");
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qemu_fdt_setprop_string(fi->fdt, name->str, "name", "lpt");
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g_string_printf(name, "%s/fdc@i3f0", fi->path);
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qemu_fdt_add_subnode(fi->fdt, name->str);
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qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
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cells[0] = cpu_to_be32(6);
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cells[1] = 0;
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qemu_fdt_setprop(fi->fdt, name->str, "interrupts",
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cells, 2 * sizeof(cells[0]));
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cells[0] = cpu_to_be32(1);
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cells[1] = cpu_to_be32(0x3f0);
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cells[2] = cpu_to_be32(8);
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qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
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qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "fdc");
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qemu_fdt_setprop_string(fi->fdt, name->str, "name", "fdc");
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g_string_printf(name, "%s/timer@i40", fi->path);
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qemu_fdt_add_subnode(fi->fdt, name->str);
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qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
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cells[0] = cpu_to_be32(1);
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cells[1] = cpu_to_be32(0x40);
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cells[2] = cpu_to_be32(8);
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qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
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qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "timer");
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qemu_fdt_setprop_string(fi->fdt, name->str, "name", "timer");
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g_string_printf(name, "%s/rtc@i70", fi->path);
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qemu_fdt_add_subnode(fi->fdt, name->str);
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qemu_fdt_setprop_string(fi->fdt, name->str, "compatible", "ds1385-rtc");
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qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
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cells[0] = cpu_to_be32(8);
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cells[1] = 0;
|
||||
qemu_fdt_setprop(fi->fdt, name->str, "interrupts",
|
||||
cells, 2 * sizeof(cells[0]));
|
||||
cells[0] = cpu_to_be32(1);
|
||||
cells[1] = cpu_to_be32(0x70);
|
||||
cells[2] = cpu_to_be32(2);
|
||||
qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
|
||||
qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "rtc");
|
||||
qemu_fdt_setprop_string(fi->fdt, name->str, "name", "rtc");
|
||||
|
||||
g_string_printf(name, "%s/keyboard@i60", fi->path);
|
||||
qemu_fdt_add_subnode(fi->fdt, name->str);
|
||||
cells[0] = cpu_to_be32(1);
|
||||
cells[1] = 0;
|
||||
qemu_fdt_setprop(fi->fdt, name->str, "interrupts",
|
||||
cells, 2 * sizeof(cells[0]));
|
||||
cells[0] = cpu_to_be32(1);
|
||||
cells[1] = cpu_to_be32(0x60);
|
||||
cells[2] = cpu_to_be32(5);
|
||||
qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
|
||||
qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "keyboard");
|
||||
qemu_fdt_setprop_string(fi->fdt, name->str, "name", "keyboard");
|
||||
|
||||
g_string_printf(name, "%s/8042@i60", fi->path);
|
||||
qemu_fdt_add_subnode(fi->fdt, name->str);
|
||||
qemu_fdt_setprop_cell(fi->fdt, name->str, "#interrupt-cells", 2);
|
||||
qemu_fdt_setprop_cell(fi->fdt, name->str, "#size-cells", 0);
|
||||
qemu_fdt_setprop_cell(fi->fdt, name->str, "#address-cells", 1);
|
||||
qemu_fdt_setprop_string(fi->fdt, name->str, "interrupt-controller", "");
|
||||
qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
|
||||
cells[0] = cpu_to_be32(1);
|
||||
cells[1] = cpu_to_be32(0x60);
|
||||
cells[2] = cpu_to_be32(5);
|
||||
qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
|
||||
qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "");
|
||||
qemu_fdt_setprop_string(fi->fdt, name->str, "name", "8042");
|
||||
|
||||
g_string_printf(name, "%s/serial@i2f8", fi->path);
|
||||
qemu_fdt_add_subnode(fi->fdt, name->str);
|
||||
qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
|
||||
cells[0] = cpu_to_be32(3);
|
||||
cells[1] = 0;
|
||||
qemu_fdt_setprop(fi->fdt, name->str, "interrupts",
|
||||
cells, 2 * sizeof(cells[0]));
|
||||
cells[0] = cpu_to_be32(1);
|
||||
cells[1] = cpu_to_be32(0x2f8);
|
||||
cells[2] = cpu_to_be32(8);
|
||||
qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
|
||||
qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "serial");
|
||||
qemu_fdt_setprop_string(fi->fdt, name->str, "name", "serial");
|
||||
|
||||
g_string_free(name, TRUE);
|
||||
}
|
||||
|
||||
static struct {
|
||||
const char *id;
|
||||
const char *name;
|
||||
void (*dtf)(PCIBus *bus, PCIDevice *d, FDTInfo *fi);
|
||||
} device_map[] = {
|
||||
{ "pci11ab,6460", "host", NULL },
|
||||
{ "pci1106,8231", "isa", dt_isa },
|
||||
{ "pci1106,571", "ide", dt_ide },
|
||||
{ "pci1106,3044", "firewire", NULL },
|
||||
{ "pci1106,3038", "usb", dt_usb },
|
||||
{ "pci1106,8235", "other", NULL },
|
||||
{ "pci1106,3058", "sound", NULL },
|
||||
{ NULL, NULL }
|
||||
};
|
||||
|
||||
static void add_pci_device(PCIBus *bus, PCIDevice *d, void *opaque)
|
||||
{
|
||||
FDTInfo *fi = opaque;
|
||||
GString *node = g_string_new(NULL);
|
||||
uint32_t cells[(PCI_NUM_REGIONS + 1) * 5];
|
||||
int i, j;
|
||||
const char *name = NULL;
|
||||
g_autofree const gchar *pn = g_strdup_printf("pci%x,%x",
|
||||
pci_get_word(&d->config[PCI_VENDOR_ID]),
|
||||
pci_get_word(&d->config[PCI_DEVICE_ID]));
|
||||
|
||||
for (i = 0; device_map[i].id; i++) {
|
||||
if (!strcmp(pn, device_map[i].id)) {
|
||||
name = device_map[i].name;
|
||||
break;
|
||||
}
|
||||
}
|
||||
g_string_printf(node, "%s/%s@%x", fi->path, (name ?: pn),
|
||||
PCI_SLOT(d->devfn));
|
||||
if (PCI_FUNC(d->devfn)) {
|
||||
g_string_append_printf(node, ",%x", PCI_FUNC(d->devfn));
|
||||
}
|
||||
|
||||
qemu_fdt_add_subnode(fi->fdt, node->str);
|
||||
if (device_map[i].dtf) {
|
||||
FDTInfo cfi = { fi->fdt, node->str };
|
||||
device_map[i].dtf(bus, d, &cfi);
|
||||
}
|
||||
cells[0] = cpu_to_be32(d->devfn << 8);
|
||||
cells[1] = 0;
|
||||
cells[2] = 0;
|
||||
cells[3] = 0;
|
||||
cells[4] = 0;
|
||||
j = 5;
|
||||
for (i = 0; i < PCI_NUM_REGIONS; i++) {
|
||||
if (!d->io_regions[i].size) {
|
||||
continue;
|
||||
}
|
||||
cells[j] = cpu_to_be32(d->devfn << 8 | (PCI_BASE_ADDRESS_0 + i * 4));
|
||||
if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) {
|
||||
cells[j] |= cpu_to_be32(1 << 24);
|
||||
} else {
|
||||
cells[j] |= cpu_to_be32(2 << 24);
|
||||
if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
|
||||
cells[j] |= cpu_to_be32(4 << 28);
|
||||
}
|
||||
}
|
||||
cells[j + 1] = 0;
|
||||
cells[j + 2] = 0;
|
||||
cells[j + 3] = cpu_to_be32(d->io_regions[i].size >> 32);
|
||||
cells[j + 4] = cpu_to_be32(d->io_regions[i].size);
|
||||
j += 5;
|
||||
}
|
||||
qemu_fdt_setprop(fi->fdt, node->str, "reg", cells, j * sizeof(cells[0]));
|
||||
qemu_fdt_setprop_string(fi->fdt, node->str, "name", name ?: pn);
|
||||
if (pci_get_byte(&d->config[PCI_INTERRUPT_PIN])) {
|
||||
qemu_fdt_setprop_cell(fi->fdt, node->str, "interrupts",
|
||||
pci_get_byte(&d->config[PCI_INTERRUPT_PIN]));
|
||||
}
|
||||
/* Pegasos2 firmware has subsystem-id amd subsystem-vendor-id swapped */
|
||||
qemu_fdt_setprop_cell(fi->fdt, node->str, "subsystem-vendor-id",
|
||||
pci_get_word(&d->config[PCI_SUBSYSTEM_ID]));
|
||||
qemu_fdt_setprop_cell(fi->fdt, node->str, "subsystem-id",
|
||||
pci_get_word(&d->config[PCI_SUBSYSTEM_VENDOR_ID]));
|
||||
cells[0] = pci_get_long(&d->config[PCI_CLASS_REVISION]);
|
||||
qemu_fdt_setprop_cell(fi->fdt, node->str, "class-code", cells[0] >> 8);
|
||||
qemu_fdt_setprop_cell(fi->fdt, node->str, "revision-id", cells[0] && 0xff);
|
||||
qemu_fdt_setprop_cell(fi->fdt, node->str, "device-id",
|
||||
pci_get_word(&d->config[PCI_DEVICE_ID]));
|
||||
qemu_fdt_setprop_cell(fi->fdt, node->str, "vendor-id",
|
||||
pci_get_word(&d->config[PCI_VENDOR_ID]));
|
||||
|
||||
g_string_free(node, TRUE);
|
||||
}
|
||||
|
||||
static void *build_fdt(MachineState *machine, int *fdt_size)
|
||||
{
|
||||
Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine);
|
||||
PowerPCCPU *cpu = pm->cpu;
|
||||
PCIBus *pci_bus;
|
||||
FDTInfo fi;
|
||||
uint32_t cells[16];
|
||||
void *fdt = create_device_tree(fdt_size);
|
||||
|
||||
fi.fdt = fdt;
|
||||
|
||||
/* root node */
|
||||
qemu_fdt_setprop_string(fdt, "/", "CODEGEN,description",
|
||||
"Pegasos CHRP PowerPC System");
|
||||
qemu_fdt_setprop_string(fdt, "/", "CODEGEN,board", "Pegasos2");
|
||||
qemu_fdt_setprop_string(fdt, "/", "CODEGEN,vendor", "bplan GmbH");
|
||||
qemu_fdt_setprop_string(fdt, "/", "revision", "2B");
|
||||
qemu_fdt_setprop_string(fdt, "/", "model", "Pegasos2");
|
||||
qemu_fdt_setprop_string(fdt, "/", "device_type", "chrp");
|
||||
qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 1);
|
||||
qemu_fdt_setprop_string(fdt, "/", "name", "bplan,Pegasos2");
|
||||
|
||||
/* pci@c0000000 */
|
||||
qemu_fdt_add_subnode(fdt, "/pci@c0000000");
|
||||
cells[0] = 0;
|
||||
cells[1] = 0;
|
||||
qemu_fdt_setprop(fdt, "/pci@c0000000", "bus-range",
|
||||
cells, 2 * sizeof(cells[0]));
|
||||
qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "pci-bridge-number", 1);
|
||||
cells[0] = cpu_to_be32(PCI0_MEM_BASE);
|
||||
cells[1] = cpu_to_be32(PCI0_MEM_SIZE);
|
||||
qemu_fdt_setprop(fdt, "/pci@c0000000", "reg", cells, 2 * sizeof(cells[0]));
|
||||
cells[0] = cpu_to_be32(0x01000000);
|
||||
cells[1] = 0;
|
||||
cells[2] = 0;
|
||||
cells[3] = cpu_to_be32(PCI0_IO_BASE);
|
||||
cells[4] = 0;
|
||||
cells[5] = cpu_to_be32(PCI0_IO_SIZE);
|
||||
cells[6] = cpu_to_be32(0x02000000);
|
||||
cells[7] = 0;
|
||||
cells[8] = cpu_to_be32(PCI0_MEM_BASE);
|
||||
cells[9] = cpu_to_be32(PCI0_MEM_BASE);
|
||||
cells[10] = 0;
|
||||
cells[11] = cpu_to_be32(PCI0_MEM_SIZE);
|
||||
qemu_fdt_setprop(fdt, "/pci@c0000000", "ranges",
|
||||
cells, 12 * sizeof(cells[0]));
|
||||
qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "#size-cells", 2);
|
||||
qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "#address-cells", 3);
|
||||
qemu_fdt_setprop_string(fdt, "/pci@c0000000", "device_type", "pci");
|
||||
qemu_fdt_setprop_string(fdt, "/pci@c0000000", "name", "pci");
|
||||
|
||||
fi.path = "/pci@c0000000";
|
||||
pci_bus = mv64361_get_pci_bus(pm->mv, 0);
|
||||
pci_for_each_device_reverse(pci_bus, 0, add_pci_device, &fi);
|
||||
|
||||
/* pci@80000000 */
|
||||
qemu_fdt_add_subnode(fdt, "/pci@80000000");
|
||||
cells[0] = 0;
|
||||
cells[1] = 0;
|
||||
qemu_fdt_setprop(fdt, "/pci@80000000", "bus-range",
|
||||
cells, 2 * sizeof(cells[0]));
|
||||
qemu_fdt_setprop_cell(fdt, "/pci@80000000", "pci-bridge-number", 0);
|
||||
cells[0] = cpu_to_be32(PCI1_MEM_BASE);
|
||||
cells[1] = cpu_to_be32(PCI1_MEM_SIZE);
|
||||
qemu_fdt_setprop(fdt, "/pci@80000000", "reg", cells, 2 * sizeof(cells[0]));
|
||||
qemu_fdt_setprop_cell(fdt, "/pci@80000000", "8259-interrupt-acknowledge",
|
||||
0xf1000cb4);
|
||||
cells[0] = cpu_to_be32(0x01000000);
|
||||
cells[1] = 0;
|
||||
cells[2] = 0;
|
||||
cells[3] = cpu_to_be32(PCI1_IO_BASE);
|
||||
cells[4] = 0;
|
||||
cells[5] = cpu_to_be32(PCI1_IO_SIZE);
|
||||
cells[6] = cpu_to_be32(0x02000000);
|
||||
cells[7] = 0;
|
||||
cells[8] = cpu_to_be32(PCI1_MEM_BASE);
|
||||
cells[9] = cpu_to_be32(PCI1_MEM_BASE);
|
||||
cells[10] = 0;
|
||||
cells[11] = cpu_to_be32(PCI1_MEM_SIZE);
|
||||
qemu_fdt_setprop(fdt, "/pci@80000000", "ranges",
|
||||
cells, 12 * sizeof(cells[0]));
|
||||
qemu_fdt_setprop_cell(fdt, "/pci@80000000", "#size-cells", 2);
|
||||
qemu_fdt_setprop_cell(fdt, "/pci@80000000", "#address-cells", 3);
|
||||
qemu_fdt_setprop_string(fdt, "/pci@80000000", "device_type", "pci");
|
||||
qemu_fdt_setprop_string(fdt, "/pci@80000000", "name", "pci");
|
||||
|
||||
fi.path = "/pci@80000000";
|
||||
pci_bus = mv64361_get_pci_bus(pm->mv, 1);
|
||||
pci_for_each_device_reverse(pci_bus, 0, add_pci_device, &fi);
|
||||
|
||||
qemu_fdt_add_subnode(fdt, "/failsafe");
|
||||
qemu_fdt_setprop_string(fdt, "/failsafe", "device_type", "serial");
|
||||
qemu_fdt_setprop_string(fdt, "/failsafe", "name", "failsafe");
|
||||
|
||||
/* cpus */
|
||||
qemu_fdt_add_subnode(fdt, "/cpus");
|
||||
qemu_fdt_setprop_cell(fdt, "/cpus", "#cpus", 1);
|
||||
qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1);
|
||||
qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0);
|
||||
qemu_fdt_setprop_string(fdt, "/cpus", "name", "cpus");
|
||||
|
||||
/* FIXME Get CPU name from CPU object */
|
||||
const char *cp = "/cpus/PowerPC,G4";
|
||||
qemu_fdt_add_subnode(fdt, cp);
|
||||
qemu_fdt_setprop_cell(fdt, cp, "l2cr", 0);
|
||||
qemu_fdt_setprop_cell(fdt, cp, "d-cache-size", 0x8000);
|
||||
qemu_fdt_setprop_cell(fdt, cp, "d-cache-block-size",
|
||||
cpu->env.dcache_line_size);
|
||||
qemu_fdt_setprop_cell(fdt, cp, "d-cache-line-size",
|
||||
cpu->env.dcache_line_size);
|
||||
qemu_fdt_setprop_cell(fdt, cp, "i-cache-size", 0x8000);
|
||||
qemu_fdt_setprop_cell(fdt, cp, "i-cache-block-size",
|
||||
cpu->env.icache_line_size);
|
||||
qemu_fdt_setprop_cell(fdt, cp, "i-cache-line-size",
|
||||
cpu->env.icache_line_size);
|
||||
if (cpu->env.id_tlbs) {
|
||||
qemu_fdt_setprop_cell(fdt, cp, "i-tlb-sets", cpu->env.nb_ways);
|
||||
qemu_fdt_setprop_cell(fdt, cp, "i-tlb-size", cpu->env.tlb_per_way);
|
||||
qemu_fdt_setprop_cell(fdt, cp, "d-tlb-sets", cpu->env.nb_ways);
|
||||
qemu_fdt_setprop_cell(fdt, cp, "d-tlb-size", cpu->env.tlb_per_way);
|
||||
qemu_fdt_setprop_string(fdt, cp, "tlb-split", "");
|
||||
}
|
||||
qemu_fdt_setprop_cell(fdt, cp, "tlb-sets", cpu->env.nb_ways);
|
||||
qemu_fdt_setprop_cell(fdt, cp, "tlb-size", cpu->env.nb_tlb);
|
||||
qemu_fdt_setprop_string(fdt, cp, "state", "running");
|
||||
if (cpu->env.insns_flags & PPC_ALTIVEC) {
|
||||
qemu_fdt_setprop_string(fdt, cp, "altivec", "");
|
||||
qemu_fdt_setprop_string(fdt, cp, "data-streams", "");
|
||||
}
|
||||
/*
|
||||
* FIXME What flags do data-streams, external-control and
|
||||
* performance-monitor depend on?
|
||||
*/
|
||||
qemu_fdt_setprop_string(fdt, cp, "external-control", "");
|
||||
if (cpu->env.insns_flags & PPC_FLOAT_FSQRT) {
|
||||
qemu_fdt_setprop_string(fdt, cp, "general-purpose", "");
|
||||
}
|
||||
qemu_fdt_setprop_string(fdt, cp, "performance-monitor", "");
|
||||
if (cpu->env.insns_flags & PPC_FLOAT_FRES) {
|
||||
qemu_fdt_setprop_string(fdt, cp, "graphics", "");
|
||||
}
|
||||
qemu_fdt_setprop_cell(fdt, cp, "reservation-granule-size", 4);
|
||||
qemu_fdt_setprop_cell(fdt, cp, "timebase-frequency",
|
||||
cpu->env.tb_env->tb_freq);
|
||||
qemu_fdt_setprop_cell(fdt, cp, "bus-frequency", BUS_FREQ_HZ);
|
||||
qemu_fdt_setprop_cell(fdt, cp, "clock-frequency", BUS_FREQ_HZ * 7.5);
|
||||
qemu_fdt_setprop_cell(fdt, cp, "cpu-version", cpu->env.spr[SPR_PVR]);
|
||||
cells[0] = 0;
|
||||
cells[1] = 0;
|
||||
qemu_fdt_setprop(fdt, cp, "reg", cells, 2 * sizeof(cells[0]));
|
||||
qemu_fdt_setprop_string(fdt, cp, "device_type", "cpu");
|
||||
qemu_fdt_setprop_string(fdt, cp, "name", strrchr(cp, '/') + 1);
|
||||
|
||||
/* memory */
|
||||
qemu_fdt_add_subnode(fdt, "/memory@0");
|
||||
cells[0] = 0;
|
||||
cells[1] = cpu_to_be32(machine->ram_size);
|
||||
qemu_fdt_setprop(fdt, "/memory@0", "reg", cells, 2 * sizeof(cells[0]));
|
||||
qemu_fdt_setprop_string(fdt, "/memory@0", "device_type", "memory");
|
||||
qemu_fdt_setprop_string(fdt, "/memory@0", "name", "memory");
|
||||
|
||||
qemu_fdt_add_subnode(fdt, "/chosen");
|
||||
qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
|
||||
machine->kernel_cmdline ?: "");
|
||||
qemu_fdt_setprop_string(fdt, "/chosen", "name", "chosen");
|
||||
|
||||
qemu_fdt_add_subnode(fdt, "/openprom");
|
||||
qemu_fdt_setprop_string(fdt, "/openprom", "model", "Pegasos2,1.1");
|
||||
|
||||
return fdt;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue