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disas/mips: Fix branch displacement for BEQZC and BNEZC

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disas/mips.c got added in commit 6643d27ea0 ("MIPS disas support")
apparently based on binutils tag 'gdb_6_1-branchpoint' [1].
Back then, MIPSr6 was not supported (added in binutils commit
7361da2c952 during 2014 [2]).

Binutils codebase diverged so much over the last 18 years, it is
not possible to simply cherry-pick their changes, so fix it BEQZC /
BNEZC 21-bit signed branch displacement locally.

[1] https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=opcodes/mips-dis.c;hb=refs/tags/gdb_6_1-branchpoint
[2] https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=7361da2c952

Fixes: 31837be3ee ("target-mips: add compact and CP1 branches")
Signed-off-by: David Daney <david.daney@fungible.com>
Reviewed-by: Marcin Nowakowski <marcin.nowakowski@fungible.com>
[PMD: Added commit description]
Signed-off-by: Philippe Mathieu-Daudé <philmd@fungible.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221014112322.61119-1-philmd@fungible.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
David Daney 2022-10-14 13:23:22 +02:00 committed by Philippe Mathieu-Daudé
parent 2413e000bb
commit a6d89b454c
1 changed files with 10 additions and 2 deletions
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12
disas/mips.c
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@ -20,6 +20,7 @@ You should have received a copy of the GNU General Public License
along with this program; if not, see <http://www.gnu.org/licenses/>. */ along with this program; if not, see <http://www.gnu.org/licenses/>. */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/bitops.h"
#include "disas/dis-asm.h" #include "disas/dis-asm.h"
/* mips.h. Mips opcode list for GDB, the GNU debugger. /* mips.h. Mips opcode list for GDB, the GNU debugger.
@ -1334,9 +1335,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"balc", "+p", 0xe8000000, 0xfc000000, UBD|WR_31, 0, I32R6}, {"balc", "+p", 0xe8000000, 0xfc000000, UBD|WR_31, 0, I32R6},
{"bc", "+p", 0xc8000000, 0xfc000000, UBD|WR_31, 0, I32R6}, {"bc", "+p", 0xc8000000, 0xfc000000, UBD|WR_31, 0, I32R6},
{"jic", "t,o", 0xd8000000, 0xffe00000, UBD|RD_t, 0, I32R6}, {"jic", "t,o", 0xd8000000, 0xffe00000, UBD|RD_t, 0, I32R6},
{"beqzc", "s,+p", 0xd8000000, 0xfc000000, CBD|RD_s, 0, I32R6}, {"beqzc", "s,+q", 0xd8000000, 0xfc000000, CBD|RD_s, 0, I32R6},
{"jialc", "t,o", 0xf8000000, 0xffe00000, UBD|RD_t, 0, I32R6}, {"jialc", "t,o", 0xf8000000, 0xffe00000, UBD|RD_t, 0, I32R6},
{"bnezc", "s,+p", 0xf8000000, 0xfc000000, CBD|RD_s, 0, I32R6}, {"bnezc", "s,+q", 0xf8000000, 0xfc000000, CBD|RD_s, 0, I32R6},
{"beqzalc", "s,t,p", 0x20000000, 0xffe00000, CBD|RD_s|RD_t, 0, I32R6}, {"beqzalc", "s,t,p", 0x20000000, 0xffe00000, CBD|RD_s|RD_t, 0, I32R6},
{"bovc", "s,t,p", 0x20000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6}, {"bovc", "s,t,p", 0x20000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
{"beqc", "s,t,p", 0x20000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6}, {"beqc", "s,t,p", 0x20000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
@ -4462,6 +4463,13 @@ print_insn_args (const char *d,
(*info->print_address_func) (info->target, info); (*info->print_address_func) (info->target, info);
break; break;
case 'q':
/* Sign extend the displacement with 21 bits. */
delta = sextract32(l, OP_SH_DELTA, 21);
info->target = (delta << 2) + pc + INSNLEN;
(*info->print_address_func) (info->target, info);
break;
case 't': /* Coprocessor 0 reg name */ case 't': /* Coprocessor 0 reg name */
(*info->fprintf_func) (info->stream, "%s", (*info->fprintf_func) (info->stream, "%s",
mips_cp0_names[(l >> OP_SH_RT) & mips_cp0_names[(l >> OP_SH_RT) &