hw/riscv: spike: Allow creating multiple NUMA sockets
We extend RISC-V spike machine to allow creating a multi-socket machine. Each RISC-V spike machine socket is a NUMA node having a set of HARTs, a memory instance, and a CLINT instance. Other devices are shared between all sockets. We also update the generated device tree accordingly. By default, NUMA multi-socket support is disabled for RISC-V spike machine. To enable it, users can use "-numa" command-line options of QEMU. Example1: For two NUMA nodes with 2 CPUs each, append following to command-line options: "-smp 4 -numa node -numa node" Example2: For two NUMA nodes with 1 and 3 CPUs, append following to command-line options: "-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \ -numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \ -numa cpu,node-id=1,core-id=3" The maximum number of sockets in a RISC-V spike machine is 8 but this limit can be changed in future. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Message-Id: <20200616032229.766089-5-anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Anup Patel
Alistair Francis
parent
83fcaefd9d
commit
a7172791e3
234
hw/riscv/spike.c
234
hw/riscv/spike.c
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@ -36,6 +36,7 @@
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#include "hw/riscv/sifive_clint.h"
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#include "hw/riscv/spike.h"
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#include "hw/riscv/boot.h"
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#include "hw/riscv/numa.h"
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#include "chardev/char.h"
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#include "sysemu/arch_init.h"
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#include "sysemu/device_tree.h"
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@ -66,9 +67,14 @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
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uint64_t mem_size, const char *cmdline)
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{
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void *fdt;
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int cpu;
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uint32_t *cells;
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char *nodename;
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uint64_t addr, size;
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unsigned long clint_addr;
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int cpu, socket;
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MachineState *mc = MACHINE(s);
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uint32_t *clint_cells;
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uint32_t cpu_phandle, intc_phandle, phandle = 1;
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char *name, *mem_name, *clint_name, *clust_name;
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char *core_name, *cpu_name, *intc_name;
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fdt = s->fdt = create_device_tree(&s->fdt_size);
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if (!fdt) {
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@ -90,68 +96,91 @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
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qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
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qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
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nodename = g_strdup_printf("/memory@%lx",
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(long)memmap[SPIKE_DRAM].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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memmap[SPIKE_DRAM].base >> 32, memmap[SPIKE_DRAM].base,
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mem_size >> 32, mem_size);
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qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
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g_free(nodename);
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qemu_fdt_add_subnode(fdt, "/cpus");
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qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
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SIFIVE_CLINT_TIMEBASE_FREQ);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
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qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
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for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
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nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
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char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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char *isa = riscv_isa_string(&s->soc.harts[cpu]);
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qemu_fdt_add_subnode(fdt, nodename);
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for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
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clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
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qemu_fdt_add_subnode(fdt, clust_name);
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clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
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for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
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cpu_phandle = phandle++;
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cpu_name = g_strdup_printf("/cpus/cpu@%d",
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s->soc[socket].hartid_base + cpu);
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qemu_fdt_add_subnode(fdt, cpu_name);
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#if defined(TARGET_RISCV32)
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qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
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qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32");
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#else
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qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
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qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48");
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#endif
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qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
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qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
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qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
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qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
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qemu_fdt_add_subnode(fdt, intc);
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qemu_fdt_setprop_cell(fdt, intc, "phandle", 1);
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qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
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qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
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qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
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g_free(isa);
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g_free(intc);
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g_free(nodename);
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name = riscv_isa_string(&s->soc[socket].harts[cpu]);
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qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name);
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g_free(name);
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qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv");
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qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
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qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
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s->soc[socket].hartid_base + cpu);
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qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
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riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket);
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qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle);
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intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
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qemu_fdt_add_subnode(fdt, intc_name);
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intc_phandle = phandle++;
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qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle);
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qemu_fdt_setprop_string(fdt, intc_name, "compatible",
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"riscv,cpu-intc");
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qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0);
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qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1);
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clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
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clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
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clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
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clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
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core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
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qemu_fdt_add_subnode(fdt, core_name);
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qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle);
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g_free(core_name);
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g_free(intc_name);
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g_free(cpu_name);
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}
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addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(mc, socket);
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size = riscv_socket_mem_size(mc, socket);
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mem_name = g_strdup_printf("/memory@%lx", (long)addr);
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qemu_fdt_add_subnode(fdt, mem_name);
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qemu_fdt_setprop_cells(fdt, mem_name, "reg",
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addr >> 32, addr, size >> 32, size);
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qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory");
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riscv_socket_fdt_write_id(mc, fdt, mem_name, socket);
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g_free(mem_name);
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clint_addr = memmap[SPIKE_CLINT].base +
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(memmap[SPIKE_CLINT].size * socket);
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clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
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qemu_fdt_add_subnode(fdt, clint_name);
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qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0");
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qemu_fdt_setprop_cells(fdt, clint_name, "reg",
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0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size);
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qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
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clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
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riscv_socket_fdt_write_id(mc, fdt, clint_name, socket);
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g_free(clint_name);
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g_free(clint_cells);
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g_free(clust_name);
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}
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cells = g_new0(uint32_t, s->soc.num_harts * 4);
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for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
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nodename =
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g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
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cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
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cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
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g_free(nodename);
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}
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nodename = g_strdup_printf("/soc/clint@%lx",
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(long)memmap[SPIKE_CLINT].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[SPIKE_CLINT].base,
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0x0, memmap[SPIKE_CLINT].size);
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qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
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cells, s->soc.num_harts * sizeof(uint32_t) * 4);
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g_free(cells);
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g_free(nodename);
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riscv_socket_fdt_write_distance_matrix(mc, fdt);
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if (cmdline) {
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qemu_fdt_add_subnode(fdt, "/chosen");
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@ -162,23 +191,59 @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
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static void spike_board_init(MachineState *machine)
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{
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const struct MemmapEntry *memmap = spike_memmap;
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SpikeState *s = g_new0(SpikeState, 1);
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SpikeState *s = SPIKE_MACHINE(machine);
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MemoryRegion *system_memory = get_system_memory();
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MemoryRegion *main_mem = g_new(MemoryRegion, 1);
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MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
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unsigned int smp_cpus = machine->smp.cpus;
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uint32_t fdt_load_addr;
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uint64_t kernel_entry;
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char *soc_name;
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int i, base_hartid, hart_count;
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/* Initialize SOC */
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object_initialize_child(OBJECT(machine), "soc", &s->soc,
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TYPE_RISCV_HART_ARRAY);
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object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type,
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&error_abort);
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object_property_set_int(OBJECT(&s->soc), "num-harts", smp_cpus,
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&error_abort);
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sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_abort);
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/* Check socket count limit */
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if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) {
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error_report("number of sockets/nodes should be less than %d",
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SPIKE_SOCKETS_MAX);
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exit(1);
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}
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/* Initialize sockets */
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for (i = 0; i < riscv_socket_count(machine); i++) {
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if (!riscv_socket_check_hartids(machine, i)) {
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error_report("discontinuous hartids in socket%d", i);
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exit(1);
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}
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base_hartid = riscv_socket_first_hartid(machine, i);
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if (base_hartid < 0) {
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error_report("can't find hartid base for socket%d", i);
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exit(1);
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}
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hart_count = riscv_socket_hart_count(machine, i);
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if (hart_count < 0) {
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error_report("can't find hart count for socket%d", i);
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exit(1);
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}
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soc_name = g_strdup_printf("soc%d", i);
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object_initialize_child(OBJECT(machine), soc_name, &s->soc[i],
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TYPE_RISCV_HART_ARRAY);
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g_free(soc_name);
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object_property_set_str(OBJECT(&s->soc[i]), "cpu-type",
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machine->cpu_type, &error_abort);
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object_property_set_int(OBJECT(&s->soc[i]), "hartid-base",
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base_hartid, &error_abort);
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object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
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hart_count, &error_abort);
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sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
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/* Core Local Interruptor (timer and IPI) for each socket */
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sifive_clint_create(
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memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size,
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memmap[SPIKE_CLINT].size, base_hartid, hart_count,
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SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
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}
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/* register system main memory (actual RAM) */
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memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
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@ -230,21 +295,40 @@ static void spike_board_init(MachineState *machine)
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fdt_load_addr, s->fdt);
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/* initialize HTIF using symbols found in load_kernel */
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htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
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/* Core Local Interruptor (timer and IPI) */
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sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
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0, smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
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false);
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htif_mm_init(system_memory, mask_rom,
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&s->soc[0].harts[0].env, serial_hd(0));
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}
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static void spike_machine_init(MachineClass *mc)
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static void spike_machine_instance_init(Object *obj)
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{
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mc->desc = "RISC-V Spike Board";
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}
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static void spike_machine_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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mc->desc = "RISC-V Spike board";
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mc->init = spike_board_init;
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mc->max_cpus = 8;
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mc->max_cpus = SPIKE_CPUS_MAX;
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mc->is_default = true;
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mc->default_cpu_type = SPIKE_V1_10_0_CPU;
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mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
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mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
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mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
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mc->numa_mem_supported = true;
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}
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DEFINE_MACHINE("spike", spike_machine_init)
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static const TypeInfo spike_machine_typeinfo = {
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.name = MACHINE_TYPE_NAME("spike"),
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.parent = TYPE_MACHINE,
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.class_init = spike_machine_class_init,
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.instance_init = spike_machine_instance_init,
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.instance_size = sizeof(SpikeState),
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};
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static void spike_machine_init_register_types(void)
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{
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type_register_static(&spike_machine_typeinfo);
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}
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type_init(spike_machine_init_register_types)
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@ -22,12 +22,19 @@
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#include "hw/riscv/riscv_hart.h"
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#include "hw/sysbus.h"
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#define SPIKE_CPUS_MAX 8
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#define SPIKE_SOCKETS_MAX 8
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#define TYPE_SPIKE_MACHINE MACHINE_TYPE_NAME("spike")
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#define SPIKE_MACHINE(obj) \
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OBJECT_CHECK(SpikeState, (obj), TYPE_SPIKE_MACHINE)
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typedef struct {
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/*< private >*/
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SysBusDevice parent_obj;
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MachineState parent;
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/*< public >*/
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RISCVHartArrayState soc;
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RISCVHartArrayState soc[SPIKE_SOCKETS_MAX];
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void *fdt;
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int fdt_size;
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} SpikeState;
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