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mips: malta/boston: replace cpu_model with cpu_type 

Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1507211474-188400-37-git-send-email-imammedo@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
This commit is contained in:
Igor Mammedov 2017-10-05 15:51:10 +02:00 committed by Eduardo Habkost
parent 81491c2846
commit a7519f2b39
8 changed files with 36 additions and 56 deletions
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11
hw/mips/boston.c
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@ -437,7 +437,6 @@ static void boston_mach_init(MachineState *machine)
DeviceState *dev;
BostonState *s;
Error *err = NULL;
const char *cpu_model;
MemoryRegion *flash, *ddr, *ddr_low_alias, *lcd, *platreg;
MemoryRegion *sys_mem = get_system_memory();
XilinxPCIEHost *pcie2;
@ -453,25 +452,24 @@ static void boston_mach_init(MachineState *machine)
exit(1);
}
cpu_model = machine->cpu_model ?: "I6400";
dev = qdev_create(NULL, TYPE_MIPS_BOSTON);
qdev_init_nofail(dev);
s = BOSTON(dev);
s->mach = machine;
if (!cpu_supports_cps_smp(cpu_model)) {
if (!cpu_supports_cps_smp(machine->cpu_type)) {
error_report("Boston requires CPUs which support CPS");
exit(1);
}
is_64b = cpu_supports_isa(cpu_model, ISA_MIPS64);
is_64b = cpu_supports_isa(machine->cpu_type, ISA_MIPS64);
s->cps = MIPS_CPS(object_new(TYPE_MIPS_CPS));
qdev_set_parent_bus(DEVICE(s->cps), sysbus_get_default());
object_property_set_str(OBJECT(s->cps), cpu_model, "cpu-model", &err);
object_property_set_str(OBJECT(s->cps), machine->cpu_type, "cpu-type",
&err);
object_property_set_int(OBJECT(s->cps), smp_cpus, "num-vp", &err);
object_property_set_bool(OBJECT(s->cps), true, "realized", &err);
@ -571,6 +569,7 @@ static void boston_mach_class_init(MachineClass *mc)
mc->block_default_type = IF_IDE;
mc->default_ram_size = 1 * G_BYTE;
mc->max_cpus = 16;
mc->default_cpu_type = MIPS_CPU_TYPE_NAME("I6400");
}
DEFINE_MACHINE("boston", boston_mach_class_init)

4
hw/mips/cps.c
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@ -71,7 +71,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
bool itu_present = false;
for (i = 0; i < s->num_vp; i++) {
cpu = MIPS_CPU(cpu_generic_init(TYPE_MIPS_CPU, s->cpu_model));
cpu = MIPS_CPU(cpu_create(s->cpu_type));
/* Init internal devices */
cpu_mips_irq_init_cpu(cpu);
@ -160,7 +160,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
static Property mips_cps_properties[] = {
DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1),
DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 256),
DEFINE_PROP_STRING("cpu-model", MIPSCPSState, cpu_model),
DEFINE_PROP_STRING("cpu-type", MIPSCPSState, cpu_type),
DEFINE_PROP_END_OF_LIST()
};

33
hw/mips/mips_malta.c
View File

@ -923,7 +923,7 @@ static void main_cpu_reset(void *opaque)
}
}
static void create_cpu_without_cps(const char *cpu_model,
static void create_cpu_without_cps(const char *cpu_type,
qemu_irq *cbus_irq, qemu_irq *i8259_irq)
{
CPUMIPSState *env;
@ -931,7 +931,7 @@ static void create_cpu_without_cps(const char *cpu_model,
int i;
for (i = 0; i < smp_cpus; i++) {
cpu = MIPS_CPU(cpu_generic_init(TYPE_MIPS_CPU, cpu_model));
cpu = MIPS_CPU(cpu_create(cpu_type));
/* Init internal devices */
cpu_mips_irq_init_cpu(cpu);
@ -945,7 +945,7 @@ static void create_cpu_without_cps(const char *cpu_model,
*cbus_irq = env->irq[4];
}
static void create_cps(MaltaState *s, const char *cpu_model,
static void create_cps(MaltaState *s, const char *cpu_type,
qemu_irq *cbus_irq, qemu_irq *i8259_irq)
{
Error *err = NULL;
@ -953,7 +953,7 @@ static void create_cps(MaltaState *s, const char *cpu_model,
s->cps = MIPS_CPS(object_new(TYPE_MIPS_CPS));
qdev_set_parent_bus(DEVICE(s->cps), sysbus_get_default());
object_property_set_str(OBJECT(s->cps), cpu_model, "cpu-model", &err);
object_property_set_str(OBJECT(s->cps), cpu_type, "cpu-type", &err);
object_property_set_int(OBJECT(s->cps), smp_cpus, "num-vp", &err);
object_property_set_bool(OBJECT(s->cps), true, "realized", &err);
if (err != NULL) {
@ -967,21 +967,13 @@ static void create_cps(MaltaState *s, const char *cpu_model,
*cbus_irq = NULL;
}
static void create_cpu(MaltaState *s, const char *cpu_model,
qemu_irq *cbus_irq, qemu_irq *i8259_irq)
static void mips_create_cpu(MaltaState *s, const char *cpu_type,
qemu_irq *cbus_irq, qemu_irq *i8259_irq)
{
if (cpu_model == NULL) {
#ifdef TARGET_MIPS64
cpu_model = "20Kc";
#else
cpu_model = "24Kf";
#endif
}
if ((smp_cpus > 1) && cpu_supports_cps_smp(cpu_model)) {
create_cps(s, cpu_model, cbus_irq, i8259_irq);
if ((smp_cpus > 1) && cpu_supports_cps_smp(cpu_type)) {
create_cps(s, cpu_type, cbus_irq, i8259_irq);
} else {
create_cpu_without_cps(cpu_model, cbus_irq, i8259_irq);
create_cpu_without_cps(cpu_type, cbus_irq, i8259_irq);
}
}
@ -1038,7 +1030,7 @@ void mips_malta_init(MachineState *machine)
}
/* create CPU */
create_cpu(s, machine->cpu_model, &cbus_irq, &i8259_irq);
mips_create_cpu(s, machine->cpu_type, &cbus_irq, &i8259_irq);
/* allocate RAM */
if (ram_size > (2048u << 20)) {
@ -1264,6 +1256,11 @@ static void mips_malta_machine_init(MachineClass *mc)
mc->block_default_type = IF_IDE;
mc->max_cpus = 16;
mc->is_default = 1;
#ifdef TARGET_MIPS64
mc->default_cpu_type = MIPS_CPU_TYPE_NAME("20Kc");
#else
mc->default_cpu_type = MIPS_CPU_TYPE_NAME("24Kf");
#endif
}
DEFINE_MACHINE("malta", mips_malta_machine_init)

2
include/hw/mips/cps.h
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@ -34,7 +34,7 @@ typedef struct MIPSCPSState {
uint32_t num_vp;
uint32_t num_irq;
char *cpu_model;
char *cpu_type;
MemoryRegion container;
MIPSGCRState gcr;

2
target/mips/cpu.c
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@ -154,7 +154,7 @@ static void mips_cpu_initfn(Object *obj)
static char *mips_cpu_type_name(const char *cpu_model)
{
return g_strdup_printf("%s-" TYPE_MIPS_CPU, cpu_model);
return g_strdup_printf(MIPS_CPU_TYPE_NAME("%s"), cpu_model);
}
static ObjectClass *mips_cpu_class_by_name(const char *cpu_model)

8
target/mips/cpu.h
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@ -740,8 +740,12 @@ enum {
int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
#define cpu_init(cpu_model) cpu_generic_init(TYPE_MIPS_CPU, cpu_model)
bool cpu_supports_cps_smp(const char *cpu_model);
bool cpu_supports_isa(const char *cpu_model, unsigned int isa);
#define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU
#define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
bool cpu_supports_cps_smp(const char *cpu_type);
bool cpu_supports_isa(const char *cpu_type, unsigned int isa);
void cpu_set_exception_base(int vp_index, target_ulong address);
/* mips_int.c */

20
target/mips/translate.c
View File

@ -20512,24 +20512,16 @@ void cpu_mips_realize_env(CPUMIPSState *env)
mvp_init(env, env->cpu_model);
}
bool cpu_supports_cps_smp(const char *cpu_model)
bool cpu_supports_cps_smp(const char *cpu_type)
{
const mips_def_t *def = cpu_mips_find_by_name(cpu_model);
if (!def) {
return false;
}
return (def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
}
bool cpu_supports_isa(const char *cpu_model, unsigned int isa)
bool cpu_supports_isa(const char *cpu_type, unsigned int isa)
{
const mips_def_t *def = cpu_mips_find_by_name(cpu_model);
if (!def) {
return false;
}
return (def->insn_flags & isa) != 0;
const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
return (mcc->cpu_def->insn_flags & isa) != 0;
}
void cpu_set_exception_base(int vp_index, target_ulong address)

12
target/mips/translate_init.c
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@ -755,18 +755,6 @@ const mips_def_t mips_defs[] =
};
const int mips_defs_number = ARRAY_SIZE(mips_defs);
static const mips_def_t *cpu_mips_find_by_name (const char *name)
{
int i;
for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
if (strcasecmp(name, mips_defs[i].name) == 0) {
return &mips_defs[i];
}
}
return NULL;
}
void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf)
{
int i;