target-ppc: fix access_type usage
Write env->access_type before a load/store operation instead of relying on the name of the dyngen operation. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5785 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32
parent
0c8aacd466
commit
a7859e892b
@ -67,6 +67,7 @@ static TCGv cpu_ctr;
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static TCGv cpu_lr;
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static TCGv cpu_xer;
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static TCGv_i32 cpu_fpscr;
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static TCGv_i32 cpu_access_type;
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/* dyngen register indexes */
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static TCGv cpu_T[3];
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@ -186,6 +187,9 @@ void ppc_translate_init(void)
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cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUState, fpscr), "fpscr");
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cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUState, access_type), "access_type");
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/* register helpers */
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#define GEN_HELPER 2
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#include "helper.h"
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@ -281,6 +285,11 @@ static always_inline void gen_optimize_fprf (void)
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#endif
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}
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static always_inline void gen_set_access_type(int access_type)
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{
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tcg_gen_movi_i32(cpu_access_type, access_type);
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}
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static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
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{
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#if defined(TARGET_PPC64)
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@ -2780,6 +2789,7 @@ static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
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GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
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{ \
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TCGv EA = tcg_temp_new(); \
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gen_set_access_type(ACCESS_INT); \
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gen_addr_imm_index(EA, ctx, 0); \
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gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
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tcg_temp_free(EA); \
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@ -2795,6 +2805,7 @@ GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
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return; \
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} \
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EA = tcg_temp_new(); \
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gen_set_access_type(ACCESS_INT); \
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if (type == PPC_64B) \
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gen_addr_imm_index(EA, ctx, 0x03); \
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else \
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@ -2814,6 +2825,7 @@ GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
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return; \
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} \
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EA = tcg_temp_new(); \
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gen_set_access_type(ACCESS_INT); \
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gen_addr_reg_index(EA, ctx); \
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gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
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tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
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@ -2824,6 +2836,7 @@ GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
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GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
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{ \
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TCGv EA = tcg_temp_new(); \
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gen_set_access_type(ACCESS_INT); \
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gen_addr_reg_index(EA, ctx); \
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gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
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tcg_temp_free(EA); \
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@ -2863,6 +2876,7 @@ GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
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}
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}
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EA = tcg_temp_new();
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gen_set_access_type(ACCESS_INT);
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gen_addr_imm_index(EA, ctx, 0x03);
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if (ctx->opcode & 0x02) {
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/* lwa (lwau is undefined) */
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@ -2901,6 +2915,7 @@ GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
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return;
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}
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EA = tcg_temp_new();
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gen_set_access_type(ACCESS_INT);
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gen_addr_imm_index(EA, ctx, 0x0F);
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gen_qemu_ld64(cpu_gpr[rd], EA, ctx->mem_idx);
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tcg_gen_addi_tl(EA, EA, 8);
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@ -2915,6 +2930,7 @@ GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
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GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
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{ \
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TCGv EA = tcg_temp_new(); \
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gen_set_access_type(ACCESS_INT); \
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gen_addr_imm_index(EA, ctx, 0); \
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gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
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tcg_temp_free(EA); \
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@ -2929,6 +2945,7 @@ GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type) \
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return; \
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} \
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EA = tcg_temp_new(); \
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gen_set_access_type(ACCESS_INT); \
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if (type == PPC_64B) \
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gen_addr_imm_index(EA, ctx, 0x03); \
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else \
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@ -2947,6 +2964,7 @@ GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
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return; \
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} \
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EA = tcg_temp_new(); \
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gen_set_access_type(ACCESS_INT); \
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gen_addr_reg_index(EA, ctx); \
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gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
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tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
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@ -2957,6 +2975,7 @@ GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
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GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
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{ \
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TCGv EA = tcg_temp_new(); \
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gen_set_access_type(ACCESS_INT); \
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gen_addr_reg_index(EA, ctx); \
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gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
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tcg_temp_free(EA); \
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@ -3002,6 +3021,7 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
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return;
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}
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EA = tcg_temp_new();
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gen_set_access_type(ACCESS_INT);
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gen_addr_imm_index(EA, ctx, 0x03);
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gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
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tcg_gen_addi_tl(EA, EA, 8);
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@ -3017,6 +3037,7 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
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}
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}
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EA = tcg_temp_new();
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gen_set_access_type(ACCESS_INT);
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gen_addr_imm_index(EA, ctx, 0x03);
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gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
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if (Rc(ctx->opcode))
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@ -3240,6 +3261,7 @@ GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
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{
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/* NIP cannot be restored if the memory exception comes from an helper */
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gen_update_nip(ctx, ctx->nip - 4);
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gen_set_access_type(ACCESS_RES);
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gen_addr_reg_index(cpu_T[0], ctx);
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op_lwarx();
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tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
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@ -3250,6 +3272,7 @@ GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
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{
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/* NIP cannot be restored if the memory exception comes from an helper */
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gen_update_nip(ctx, ctx->nip - 4);
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gen_set_access_type(ACCESS_RES);
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gen_addr_reg_index(cpu_T[0], ctx);
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tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
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op_stwcx();
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@ -3270,6 +3293,7 @@ GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
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{
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/* NIP cannot be restored if the memory exception comes from an helper */
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gen_update_nip(ctx, ctx->nip - 4);
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gen_set_access_type(ACCESS_RES);
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gen_addr_reg_index(cpu_T[0], ctx);
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op_ldarx();
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tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
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@ -3280,6 +3304,7 @@ GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
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{
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/* NIP cannot be restored if the memory exception comes from an helper */
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gen_update_nip(ctx, ctx->nip - 4);
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gen_set_access_type(ACCESS_RES);
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gen_addr_reg_index(cpu_T[0], ctx);
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tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
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op_stdcx();
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@ -3307,6 +3332,7 @@ GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
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GEN_EXCP_NO_FP(ctx); \
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return; \
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} \
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gen_set_access_type(ACCESS_FLOAT); \
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gen_addr_imm_index(cpu_T[0], ctx, 0); \
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op_ldst(l##width); \
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tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
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@ -3323,6 +3349,7 @@ GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
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GEN_EXCP_INVAL(ctx); \
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return; \
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} \
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gen_set_access_type(ACCESS_FLOAT); \
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gen_addr_imm_index(cpu_T[0], ctx, 0); \
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op_ldst(l##width); \
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tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
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@ -3340,6 +3367,7 @@ GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
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GEN_EXCP_INVAL(ctx); \
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return; \
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} \
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gen_set_access_type(ACCESS_FLOAT); \
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gen_addr_reg_index(cpu_T[0], ctx); \
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op_ldst(l##width); \
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tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
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@ -3353,6 +3381,7 @@ GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
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GEN_EXCP_NO_FP(ctx); \
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return; \
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} \
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gen_set_access_type(ACCESS_FLOAT); \
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gen_addr_reg_index(cpu_T[0], ctx); \
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op_ldst(l##width); \
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tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
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@ -3378,6 +3407,7 @@ GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
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GEN_EXCP_NO_FP(ctx); \
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return; \
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} \
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gen_set_access_type(ACCESS_FLOAT); \
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gen_addr_imm_index(cpu_T[0], ctx, 0); \
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tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
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op_ldst(st##width); \
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@ -3394,6 +3424,7 @@ GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
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GEN_EXCP_INVAL(ctx); \
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return; \
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} \
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gen_set_access_type(ACCESS_FLOAT); \
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gen_addr_imm_index(cpu_T[0], ctx, 0); \
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tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
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op_ldst(st##width); \
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@ -3411,6 +3442,7 @@ GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
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GEN_EXCP_INVAL(ctx); \
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return; \
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} \
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gen_set_access_type(ACCESS_FLOAT); \
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gen_addr_reg_index(cpu_T[0], ctx); \
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tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
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op_ldst(st##width); \
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@ -3424,6 +3456,7 @@ GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
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GEN_EXCP_NO_FP(ctx); \
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return; \
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} \
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gen_set_access_type(ACCESS_FLOAT); \
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gen_addr_reg_index(cpu_T[0], ctx); \
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tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
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op_ldst(st##width); \
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@ -4011,6 +4044,7 @@ GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
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{
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/* XXX: specification says this is treated as a load by the MMU */
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TCGv t0 = tcg_temp_new();
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gen_set_access_type(ACCESS_CACHE);
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gen_addr_reg_index(t0, ctx);
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gen_qemu_ld8u(t0, t0, ctx->mem_idx);
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tcg_temp_free(t0);
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@ -4028,6 +4062,7 @@ GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
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return;
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}
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EA = tcg_temp_new();
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gen_set_access_type(ACCESS_CACHE);
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gen_addr_reg_index(EA, ctx);
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val = tcg_temp_new();
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/* XXX: specification says this should be treated as a store by the MMU */
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@ -4043,6 +4078,7 @@ GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
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{
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/* XXX: specification say this is treated as a load by the MMU */
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TCGv t0 = tcg_temp_new();
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gen_set_access_type(ACCESS_CACHE);
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gen_addr_reg_index(t0, ctx);
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gen_qemu_ld8u(t0, t0, ctx->mem_idx);
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tcg_temp_free(t0);
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@ -4428,6 +4464,7 @@ static GenOpFunc *gen_op_ecowx[NB_MEM_FUNCS] = {
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GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
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{
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/* Should check EAR[E] & alignment ! */
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gen_set_access_type(ACCESS_RES);
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gen_addr_reg_index(cpu_T[0], ctx);
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op_eciwx();
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tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
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@ -5512,6 +5549,7 @@ GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
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return;
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}
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EA = tcg_temp_new();
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gen_set_access_type(ACCESS_CACHE);
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gen_addr_reg_index(EA, ctx);
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val = tcg_temp_new();
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gen_qemu_ld32u(val, EA, ctx->mem_idx);
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@ -7630,41 +7668,5 @@ void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
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void gen_pc_load(CPUState *env, TranslationBlock *tb,
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unsigned long searched_pc, int pc_pos, void *puc)
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{
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int type, c;
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/* for PPC, we need to look at the micro operation to get the
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* access type */
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env->nip = gen_opc_pc[pc_pos];
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c = gen_opc_buf[pc_pos];
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switch(c) {
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#if defined(CONFIG_USER_ONLY)
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#define CASE3(op)\
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case INDEX_op_ ## op ## _raw
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#else
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#define CASE3(op)\
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case INDEX_op_ ## op ## _user:\
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case INDEX_op_ ## op ## _kernel:\
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case INDEX_op_ ## op ## _hypv
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#endif
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CASE3(stfd):
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CASE3(stfs):
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CASE3(lfd):
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CASE3(lfs):
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type = ACCESS_FLOAT;
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break;
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CASE3(lwarx):
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type = ACCESS_RES;
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break;
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CASE3(stwcx):
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type = ACCESS_RES;
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break;
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CASE3(eciwx):
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CASE3(ecowx):
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type = ACCESS_EXT;
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break;
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default:
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type = ACCESS_INT;
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break;
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}
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env->access_type = type;
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}
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