From a7b4569a4dddf0255d29ec56045c65f9bcb60919 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Thu, 16 Aug 2018 14:05:29 +0100 Subject: [PATCH] aspeed_sdmc: Handle ECC training MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is required to ensure u-boot SDRAM training completes. Signed-off-by: Joel Stanley Reviewed-by: Cédric Le Goater Tested-by: Cédric Le Goater Message-id: 20180807075757.7242-6-joel@jms.id.au Signed-off-by: Peter Maydell --- hw/misc/aspeed_sdmc.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c index 522e01ef8c..89de3138af 100644 --- a/hw/misc/aspeed_sdmc.c +++ b/hw/misc/aspeed_sdmc.c @@ -27,6 +27,10 @@ #define R_STATUS1 (0x60 / 4) #define PHY_BUSY_STATE BIT(0) +#define R_ECC_TEST_CTRL (0x70 / 4) +#define ECC_TEST_FINISHED BIT(12) +#define ECC_TEST_FAIL BIT(13) + /* * Configuration register Ox4 (for Aspeed AST2400 SOC) * @@ -148,6 +152,11 @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data, /* Will never return 'busy' */ data &= ~PHY_BUSY_STATE; break; + case R_ECC_TEST_CTRL: + /* Always done, always happy */ + data |= ECC_TEST_FINISHED; + data &= ~ECC_TEST_FAIL; + break; default: break; }