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Improve interrupt handling priority

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The vector interrupt has higher priority than interrupt_level_n.
Also check only interrupt_level_n concurency when TL > 0, the traps of
other types may be nested.

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Artyom Tarasenko 2012-04-03 17:49:05 +02:00 committed by Blue Swirl
parent 23cf96e197
commit a7be9bad33
1 changed files with 6 additions and 1 deletions
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7
hw/sun4u.c
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@ -248,6 +248,10 @@ void cpu_check_irqs(CPUSPARCState *env)
uint32_t pil = env->pil_in |
(env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER));
/* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */
if (env->ivec_status & 0x20) {
return;
}
/* check if TM or SM in SOFTINT are set
setting these also causes interrupt 14 */
if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
@ -275,7 +279,8 @@ void cpu_check_irqs(CPUSPARCState *env)
int old_interrupt = env->interrupt_index;
int new_interrupt = TT_EXTINT | i;
if (env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt) {
if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt
&& ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) {
CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
"current %x >= pending %x\n",
env->tl, cpu_tsptr(env)->tt, new_interrupt);