From a7f112c5fd1ac22732e523c8e933728fca681a0a Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 12 Apr 2023 13:43:17 +0200 Subject: [PATCH] target/riscv: Use cpu_ld*_code_mmu for HLVX Use the new functions to properly check execute permission for the read rather than read permission. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-10-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-10-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/op_helper.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 0adfd1ca9a..49179e7a5a 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -427,18 +427,27 @@ void helper_hyp_gvma_tlb_flush(CPURISCVState *env) helper_hyp_tlb_flush(env); } +/* + * TODO: These implementations are not quite correct. They perform the + * access using execute permission just fine, but the final PMP check + * is supposed to have read permission as well. Without replicating + * a fair fraction of cputlb.c, fixing this requires adding new mmu_idx + * which would imply that exact check in tlb_fill. + */ target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong address) { int mmu_idx = cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT; + MemOpIdx oi = make_memop_idx(MO_TEUW, mmu_idx); - return cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC()); + return cpu_ldw_code_mmu(env, address, oi, GETPC()); } target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong address) { int mmu_idx = cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT; + MemOpIdx oi = make_memop_idx(MO_TEUL, mmu_idx); - return cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); + return cpu_ldl_code_mmu(env, address, oi, GETPC()); } #endif /* !CONFIG_USER_ONLY */