cirrus: simplify vga window mmio access functions
Make use of the memory API's ability to satisfy multi-byte accesses via multiple single-byte accesses. Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
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@ -1956,7 +1956,9 @@ static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
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*
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***************************************/
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static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
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static uint64_t cirrus_vga_mem_read(void *opaque,
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target_phys_addr_t addr,
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uint32_t size)
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{
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CirrusVGAState *s = opaque;
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unsigned bank_index;
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@ -1967,8 +1969,6 @@ static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
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return vga_mem_readb(s, addr);
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}
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addr &= 0x1ffff;
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if (addr < 0x10000) {
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/* XXX handle bitblt */
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/* video memory */
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@ -2000,28 +2000,10 @@ static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
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return val;
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}
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static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
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{
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uint32_t v;
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v = cirrus_vga_mem_readb(opaque, addr);
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v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
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return v;
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}
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static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
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{
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uint32_t v;
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v = cirrus_vga_mem_readb(opaque, addr);
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v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
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v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16;
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v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24;
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return v;
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}
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static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
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uint32_t mem_value)
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static void cirrus_vga_mem_write(void *opaque,
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target_phys_addr_t addr,
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uint64_t mem_value,
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uint32_t size)
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{
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CirrusVGAState *s = opaque;
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unsigned bank_index;
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@ -2033,8 +2015,6 @@ static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
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return;
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}
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addr &= 0x1ffff;
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if (addr < 0x10000) {
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if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
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/* bitblt */
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@ -2084,51 +2064,14 @@ static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
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}
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}
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static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
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cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
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}
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static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
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cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
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cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
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cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
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}
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static uint64_t cirrus_vga_mem_read(void *opaque,
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target_phys_addr_t addr,
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uint32_t size)
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{
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CirrusVGAState *s = opaque;
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switch (size) {
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case 1: return cirrus_vga_mem_readb(s, addr);
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case 2: return cirrus_vga_mem_readw(s, addr);
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case 4: return cirrus_vga_mem_readl(s, addr);
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default: abort();
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}
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}
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static void cirrus_vga_mem_write(void *opaque, target_phys_addr_t addr,
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uint64_t data, unsigned size)
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{
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CirrusVGAState *s = opaque;
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switch (size) {
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case 1: return cirrus_vga_mem_writeb(s, addr, data);
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case 2: return cirrus_vga_mem_writew(s, addr, data);
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case 4: return cirrus_vga_mem_writel(s, addr, data);
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default: abort();
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}
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};
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static const MemoryRegionOps cirrus_vga_mem_ops = {
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.read = cirrus_vga_mem_read,
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.write = cirrus_vga_mem_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.min_access_size = 1,
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.max_access_size = 1,
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},
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};
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/***************************************
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