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Rename target_phys_addr_t to hwaddr 

target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are
reserved) and its purpose doesn't match the name (most target_phys_addr_t
addresses are not target specific).  Replace it with a finger-friendly,
standards conformant hwaddr.

Outstanding patchsets can be fixed up with the command

  git rebase -i --exec 'find -name "*.[ch]"
                        | xargs s/target_phys_addr_t/hwaddr/g' origin

Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Avi Kivity 2012-10-23 12:30:10 +02:00 committed by Anthony Liguori
parent 50d2b4d93f
commit a8170e5e97
383 changed files with 2240 additions and 2240 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
HACKING
View File

@ -32,7 +32,7 @@ mandatory for VMState fields.
Don't use Linux kernel internal types like u32, __u32 or __le32.
Use target_phys_addr_t for guest physical addresses except pcibus_t
Use hwaddr for guest physical addresses except pcibus_t
for PCI addresses. In addition, ram_addr_t is a QEMU internal address
space that maps guest RAM physical addresses into an intermediate
address space that can map to host virtual address spaces. Generally

2
cpu-all.h
View File

@ -474,7 +474,7 @@ void run_on_cpu(CPUArchState *env, void (*func)(void *data), void *data);
/* Return the physical page corresponding to a virtual one. Use it
only for debugging because no protection checks are done. Return -1
if no page found. */
target_phys_addr_t cpu_get_phys_page_debug(CPUArchState *env, target_ulong addr);
hwaddr cpu_get_phys_page_debug(CPUArchState *env, target_ulong addr);
/* memory API */

68
cpu-common.h
View File

@ -3,7 +3,7 @@
/* CPU interfaces that are target independent. */
#include "targphys.h"
#include "hwaddr.h"
#ifndef NEED_CPU_H
#include "poison.h"
@ -33,8 +33,8 @@ typedef uintptr_t ram_addr_t;
/* memory API */
typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
typedef void CPUWriteMemoryFunc(void *opaque, hwaddr addr, uint32_t value);
typedef uint32_t CPUReadMemoryFunc(void *opaque, hwaddr addr);
void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);
/* This should only be used for ram local to a device. */
@ -49,27 +49,27 @@ int qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr);
ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr);
void qemu_ram_set_idstr(ram_addr_t addr, const char *name, DeviceState *dev);
void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
int len, int is_write);
static inline void cpu_physical_memory_read(target_phys_addr_t addr,
static inline void cpu_physical_memory_read(hwaddr addr,
void *buf, int len)
{
cpu_physical_memory_rw(addr, buf, len, 0);
}
static inline void cpu_physical_memory_write(target_phys_addr_t addr,
static inline void cpu_physical_memory_write(hwaddr addr,
const void *buf, int len)
{
cpu_physical_memory_rw(addr, (void *)buf, len, 1);
}
void *cpu_physical_memory_map(target_phys_addr_t addr,
target_phys_addr_t *plen,
void *cpu_physical_memory_map(hwaddr addr,
hwaddr *plen,
int is_write);
void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
int is_write, target_phys_addr_t access_len);
void cpu_physical_memory_unmap(void *buffer, hwaddr len,
int is_write, hwaddr access_len);
void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque));
void cpu_unregister_map_client(void *cookie);
bool cpu_physical_memory_is_io(target_phys_addr_t phys_addr);
bool cpu_physical_memory_is_io(hwaddr phys_addr);
/* Coalesced MMIO regions are areas where write operations can be reordered.
* This usually implies that write operations are side-effect free. This allows
@ -78,33 +78,33 @@ bool cpu_physical_memory_is_io(target_phys_addr_t phys_addr);
*/
void qemu_flush_coalesced_mmio_buffer(void);
uint32_t ldub_phys(target_phys_addr_t addr);
uint32_t lduw_le_phys(target_phys_addr_t addr);
uint32_t lduw_be_phys(target_phys_addr_t addr);
uint32_t ldl_le_phys(target_phys_addr_t addr);
uint32_t ldl_be_phys(target_phys_addr_t addr);
uint64_t ldq_le_phys(target_phys_addr_t addr);
uint64_t ldq_be_phys(target_phys_addr_t addr);
void stb_phys(target_phys_addr_t addr, uint32_t val);
void stw_le_phys(target_phys_addr_t addr, uint32_t val);
void stw_be_phys(target_phys_addr_t addr, uint32_t val);
void stl_le_phys(target_phys_addr_t addr, uint32_t val);
void stl_be_phys(target_phys_addr_t addr, uint32_t val);
void stq_le_phys(target_phys_addr_t addr, uint64_t val);
void stq_be_phys(target_phys_addr_t addr, uint64_t val);
uint32_t ldub_phys(hwaddr addr);
uint32_t lduw_le_phys(hwaddr addr);
uint32_t lduw_be_phys(hwaddr addr);
uint32_t ldl_le_phys(hwaddr addr);
uint32_t ldl_be_phys(hwaddr addr);
uint64_t ldq_le_phys(hwaddr addr);
uint64_t ldq_be_phys(hwaddr addr);
void stb_phys(hwaddr addr, uint32_t val);
void stw_le_phys(hwaddr addr, uint32_t val);
void stw_be_phys(hwaddr addr, uint32_t val);
void stl_le_phys(hwaddr addr, uint32_t val);
void stl_be_phys(hwaddr addr, uint32_t val);
void stq_le_phys(hwaddr addr, uint64_t val);
void stq_be_phys(hwaddr addr, uint64_t val);
#ifdef NEED_CPU_H
uint32_t lduw_phys(target_phys_addr_t addr);
uint32_t ldl_phys(target_phys_addr_t addr);
uint64_t ldq_phys(target_phys_addr_t addr);
void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
void stw_phys(target_phys_addr_t addr, uint32_t val);
void stl_phys(target_phys_addr_t addr, uint32_t val);
void stq_phys(target_phys_addr_t addr, uint64_t val);
uint32_t lduw_phys(hwaddr addr);
uint32_t ldl_phys(hwaddr addr);
uint64_t ldq_phys(hwaddr addr);
void stl_phys_notdirty(hwaddr addr, uint32_t val);
void stq_phys_notdirty(hwaddr addr, uint64_t val);
void stw_phys(hwaddr addr, uint32_t val);
void stl_phys(hwaddr addr, uint32_t val);
void stq_phys(hwaddr addr, uint64_t val);
#endif
void cpu_physical_memory_write_rom(target_phys_addr_t addr,
void cpu_physical_memory_write_rom(hwaddr addr,
const uint8_t *buf, int len);
extern struct MemoryRegion io_mem_ram;

4
cpu-defs.h
View File

@ -29,7 +29,7 @@
#include <signal.h>
#include "osdep.h"
#include "qemu-queue.h"
#include "targphys.h"
#include "hwaddr.h"
#ifndef TARGET_LONG_BITS
#error TARGET_LONG_BITS must be defined before including this header
@ -111,7 +111,7 @@ extern int CPUTLBEntry_wrong_size[sizeof(CPUTLBEntry) == (1 << CPU_TLB_ENTRY_BIT
#define CPU_COMMON_TLB \
/* The meaning of the MMU modes is defined in the target code. */ \
CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
hwaddr iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
target_ulong tlb_flush_addr; \
target_ulong tlb_flush_mask;

4
cputlb.c
View File

@ -237,7 +237,7 @@ static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr,
is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
supplied size is only used by tlb_flush_page. */
void tlb_set_page(CPUArchState *env, target_ulong vaddr,
target_phys_addr_t paddr, int prot,
hwaddr paddr, int prot,
int mmu_idx, target_ulong size)
{
MemoryRegionSection *section;
@ -246,7 +246,7 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr,
target_ulong code_address;
uintptr_t addend;
CPUTLBEntry *te;
target_phys_addr_t iotlb;
hwaddr iotlb;
assert(size >= TARGET_PAGE_SIZE);
if (size != TARGET_PAGE_SIZE) {

6
cputlb.h
View File

@ -27,17 +27,17 @@ void tlb_unprotect_code_phys(CPUArchState *env, ram_addr_t ram_addr,
void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, uintptr_t start,
uintptr_t length);
MemoryRegionSection *phys_page_find(struct AddressSpaceDispatch *d,
target_phys_addr_t index);
hwaddr index);
void cpu_tlb_reset_dirty_all(ram_addr_t start1, ram_addr_t length);
void tlb_set_dirty(CPUArchState *env, target_ulong vaddr);
extern int tlb_flush_count;
/* exec.c */
void tb_flush_jmp_cache(CPUArchState *env, target_ulong addr);
target_phys_addr_t memory_region_section_get_iotlb(CPUArchState *env,
hwaddr memory_region_section_get_iotlb(CPUArchState *env,
MemoryRegionSection *section,
target_ulong vaddr,
target_phys_addr_t paddr,
hwaddr paddr,
int prot,
target_ulong *address);
bool memory_region_is_unassigned(MemoryRegion *mr);

2
disas.h
View File

@ -22,7 +22,7 @@ struct elf64_sym;
#if defined(CONFIG_USER_ONLY)
typedef const char *(*lookup_symbol_t)(struct syminfo *s, target_ulong orig_addr);
#else
typedef const char *(*lookup_symbol_t)(struct syminfo *s, target_phys_addr_t orig_addr);
typedef const char *(*lookup_symbol_t)(struct syminfo *s, hwaddr orig_addr);
#endif
struct syminfo {

8
dma-helpers.c
View File

@ -281,7 +281,7 @@ void dma_acct_start(BlockDriverState *bs, BlockAcctCookie *cookie,
bool iommu_dma_memory_valid(DMAContext *dma, dma_addr_t addr, dma_addr_t len,
DMADirection dir)
{
target_phys_addr_t paddr, plen;
hwaddr paddr, plen;
#ifdef DEBUG_IOMMU
fprintf(stderr, "dma_memory_check context=%p addr=0x" DMA_ADDR_FMT
@ -308,7 +308,7 @@ bool iommu_dma_memory_valid(DMAContext *dma, dma_addr_t addr, dma_addr_t len,
int iommu_dma_memory_rw(DMAContext *dma, dma_addr_t addr,
void *buf, dma_addr_t len, DMADirection dir)
{
target_phys_addr_t paddr, plen;
hwaddr paddr, plen;
int err;
#ifdef DEBUG_IOMMU
@ -346,7 +346,7 @@ int iommu_dma_memory_rw(DMAContext *dma, dma_addr_t addr,
int iommu_dma_memory_set(DMAContext *dma, dma_addr_t addr, uint8_t c,
dma_addr_t len)
{
target_phys_addr_t paddr, plen;
hwaddr paddr, plen;
int err;
#ifdef DEBUG_IOMMU
@ -392,7 +392,7 @@ void *iommu_dma_memory_map(DMAContext *dma, dma_addr_t addr, dma_addr_t *len,
DMADirection dir)
{
int err;
target_phys_addr_t paddr, plen;
hwaddr paddr, plen;
void *buf;
if (dma->map) {

8
dma.h
View File

@ -48,8 +48,8 @@ typedef uint64_t dma_addr_t;
typedef int DMATranslateFunc(DMAContext *dma,
dma_addr_t addr,
target_phys_addr_t *paddr,
target_phys_addr_t *len,
hwaddr *paddr,
hwaddr *len,
DMADirection dir);
typedef void* DMAMapFunc(DMAContext *dma,
dma_addr_t addr,
@ -177,7 +177,7 @@ static inline void *dma_memory_map(DMAContext *dma,
DMADirection dir)
{
if (!dma_has_iommu(dma)) {
target_phys_addr_t xlen = *len;
hwaddr xlen = *len;
void *p;
p = address_space_map(dma->as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE);
@ -196,7 +196,7 @@ static inline void dma_memory_unmap(DMAContext *dma,
DMADirection dir, dma_addr_t access_len)
{
if (!dma_has_iommu(dma)) {
address_space_unmap(dma->as, buffer, (target_phys_addr_t)len,
address_space_unmap(dma->as, buffer, (hwaddr)len,
dir == DMA_DIRECTION_FROM_DEVICE, access_len);
} else {
iommu_dma_memory_unmap(dma, buffer, len, dir, access_len);

18
dump.c
View File

@ -15,7 +15,7 @@
#include "elf.h"
#include "cpu.h"
#include "cpu-all.h"
#include "targphys.h"
#include "hwaddr.h"
#include "monitor.h"
#include "kvm.h"
#include "dump.h"
@ -66,7 +66,7 @@ typedef struct DumpState {
bool have_section;
bool resume;
size_t note_size;
target_phys_addr_t memory_offset;
hwaddr memory_offset;
int fd;
RAMBlock *block;
@ -187,7 +187,7 @@ static int write_elf32_header(DumpState *s)
}
static int write_elf64_load(DumpState *s, MemoryMapping *memory_mapping,
int phdr_index, target_phys_addr_t offset)
int phdr_index, hwaddr offset)
{
Elf64_Phdr phdr;
int ret;
@ -216,7 +216,7 @@ static int write_elf64_load(DumpState *s, MemoryMapping *memory_mapping,
}
static int write_elf32_load(DumpState *s, MemoryMapping *memory_mapping,
int phdr_index, target_phys_addr_t offset)
int phdr_index, hwaddr offset)
{
Elf32_Phdr phdr;
int ret;
@ -248,7 +248,7 @@ static int write_elf64_note(DumpState *s)
{
Elf64_Phdr phdr;
int endian = s->dump_info.d_endian;
target_phys_addr_t begin = s->memory_offset - s->note_size;
hwaddr begin = s->memory_offset - s->note_size;
int ret;
memset(&phdr, 0, sizeof(Elf64_Phdr));
@ -296,7 +296,7 @@ static int write_elf64_notes(DumpState *s)
static int write_elf32_note(DumpState *s)
{
target_phys_addr_t begin = s->memory_offset - s->note_size;
hwaddr begin = s->memory_offset - s->note_size;
Elf32_Phdr phdr;
int endian = s->dump_info.d_endian;
int ret;
@ -414,11 +414,11 @@ static int write_memory(DumpState *s, RAMBlock *block, ram_addr_t start,
}
/* get the memory's offset in the vmcore */
static target_phys_addr_t get_offset(target_phys_addr_t phys_addr,
static hwaddr get_offset(hwaddr phys_addr,
DumpState *s)
{
RAMBlock *block;
target_phys_addr_t offset = s->memory_offset;
hwaddr offset = s->memory_offset;
int64_t size_in_block, start;
if (s->has_filter) {
@ -463,7 +463,7 @@ static target_phys_addr_t get_offset(target_phys_addr_t phys_addr,
static int write_elf_loads(DumpState *s)
{
target_phys_addr_t offset;
hwaddr offset;
MemoryMapping *memory_mapping;
uint32_t phdr_index = 1;
int ret;

10
exec-all.h
View File

@ -103,9 +103,9 @@ void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end,
void tlb_flush_page(CPUArchState *env, target_ulong addr);
void tlb_flush(CPUArchState *env, int flush_global);
void tlb_set_page(CPUArchState *env, target_ulong vaddr,
target_phys_addr_t paddr, int prot,
hwaddr paddr, int prot,
int mmu_idx, target_ulong size);
void tb_invalidate_phys_addr(target_phys_addr_t addr);
void tb_invalidate_phys_addr(hwaddr addr);
#else
static inline void tlb_flush_page(CPUArchState *env, target_ulong addr)
{
@ -312,10 +312,10 @@ extern uintptr_t tci_tb_ptr;
#if !defined(CONFIG_USER_ONLY)
struct MemoryRegion *iotlb_to_region(target_phys_addr_t index);
uint64_t io_mem_read(struct MemoryRegion *mr, target_phys_addr_t addr,
struct MemoryRegion *iotlb_to_region(hwaddr index);
uint64_t io_mem_read(struct MemoryRegion *mr, hwaddr addr,
unsigned size);
void io_mem_write(struct MemoryRegion *mr, target_phys_addr_t addr,
void io_mem_write(struct MemoryRegion *mr, hwaddr addr,
uint64_t value, unsigned size);
void tlb_fill(CPUArchState *env1, target_ulong addr, int is_write, int mmu_idx,

162
exec.c
View File

@ -398,13 +398,13 @@ static void phys_map_nodes_reset(void)
}
static void phys_page_set_level(PhysPageEntry *lp, target_phys_addr_t *index,
target_phys_addr_t *nb, uint16_t leaf,
static void phys_page_set_level(PhysPageEntry *lp, hwaddr *index,
hwaddr *nb, uint16_t leaf,
int level)
{
PhysPageEntry *p;
int i;
target_phys_addr_t step = (target_phys_addr_t)1 << (level * L2_BITS);
hwaddr step = (hwaddr)1 << (level * L2_BITS);
if (!lp->is_leaf && lp->ptr == PHYS_MAP_NODE_NIL) {
lp->ptr = phys_map_node_alloc();
@ -434,7 +434,7 @@ static void phys_page_set_level(PhysPageEntry *lp, target_phys_addr_t *index,
}
static void phys_page_set(AddressSpaceDispatch *d,
target_phys_addr_t index, target_phys_addr_t nb,
hwaddr index, hwaddr nb,
uint16_t leaf)
{
/* Wildly overreserve - it doesn't matter much. */
@ -443,7 +443,7 @@ static void phys_page_set(AddressSpaceDispatch *d,
phys_page_set_level(&d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1);
}
MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, target_phys_addr_t index)
MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, hwaddr index)
{
PhysPageEntry lp = d->phys_map;
PhysPageEntry *p;
@ -1473,7 +1473,7 @@ static void breakpoint_invalidate(CPUArchState *env, target_ulong pc)
tb_invalidate_phys_page_range(pc, pc + 1, 0);
}
#else
void tb_invalidate_phys_addr(target_phys_addr_t addr)
void tb_invalidate_phys_addr(hwaddr addr)
{
ram_addr_t ram_addr;
MemoryRegionSection *section;
@ -1866,14 +1866,14 @@ int cpu_physical_memory_set_dirty_tracking(int enable)
return ret;
}
target_phys_addr_t memory_region_section_get_iotlb(CPUArchState *env,
hwaddr memory_region_section_get_iotlb(CPUArchState *env,
MemoryRegionSection *section,
target_ulong vaddr,
target_phys_addr_t paddr,
hwaddr paddr,
int prot,
target_ulong *address)
{
target_phys_addr_t iotlb;
hwaddr iotlb;
CPUWatchpoint *wp;
if (memory_region_is_ram(section->mr)) {
@ -2176,13 +2176,13 @@ int page_unprotect(target_ulong address, uintptr_t pc, void *puc)
#define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
typedef struct subpage_t {
MemoryRegion iomem;
target_phys_addr_t base;
hwaddr base;
uint16_t sub_section[TARGET_PAGE_SIZE];
} subpage_t;
static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
uint16_t section);
static subpage_t *subpage_init(target_phys_addr_t base);
static subpage_t *subpage_init(hwaddr base);
static void destroy_page_desc(uint16_t section_index)
{
MemoryRegionSection *section = &phys_sections[section_index];
@ -2241,14 +2241,14 @@ static void phys_sections_clear(void)
static void register_subpage(AddressSpaceDispatch *d, MemoryRegionSection *section)
{
subpage_t *subpage;
target_phys_addr_t base = section->offset_within_address_space
hwaddr base = section->offset_within_address_space
& TARGET_PAGE_MASK;
MemoryRegionSection *existing = phys_page_find(d, base >> TARGET_PAGE_BITS);
MemoryRegionSection subsection = {
.offset_within_address_space = base,
.size = TARGET_PAGE_SIZE,
};
target_phys_addr_t start, end;
hwaddr start, end;
assert(existing->mr->subpage || existing->mr == &io_mem_unassigned);
@ -2268,9 +2268,9 @@ static void register_subpage(AddressSpaceDispatch *d, MemoryRegionSection *secti
static void register_multipage(AddressSpaceDispatch *d, MemoryRegionSection *section)
{
target_phys_addr_t start_addr = section->offset_within_address_space;
hwaddr start_addr = section->offset_within_address_space;
ram_addr_t size = section->size;
target_phys_addr_t addr;
hwaddr addr;
uint16_t section_index = phys_section_add(section);
assert(size);
@ -2836,7 +2836,7 @@ ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr)
return ram_addr;
}
static uint64_t unassigned_mem_read(void *opaque, target_phys_addr_t addr,
static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
#ifdef DEBUG_UNASSIGNED
@ -2848,7 +2848,7 @@ static uint64_t unassigned_mem_read(void *opaque, target_phys_addr_t addr,
return 0;
}
static void unassigned_mem_write(void *opaque, target_phys_addr_t addr,
static void unassigned_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
#ifdef DEBUG_UNASSIGNED
@ -2865,13 +2865,13 @@ static const MemoryRegionOps unassigned_mem_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static uint64_t error_mem_read(void *opaque, target_phys_addr_t addr,
static uint64_t error_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
abort();
}
static void error_mem_write(void *opaque, target_phys_addr_t addr,
static void error_mem_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
abort();
@ -2889,7 +2889,7 @@ static const MemoryRegionOps rom_mem_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void notdirty_mem_write(void *opaque, target_phys_addr_t ram_addr,
static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
uint64_t val, unsigned size)
{
int dirty_flags;
@ -2976,7 +2976,7 @@ static void check_watchpoint(int offset, int len_mask, int flags)
/* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
so these check for a hit then pass through to the normal out-of-line
phys routines. */
static uint64_t watch_mem_read(void *opaque, target_phys_addr_t addr,
static uint64_t watch_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_READ);
@ -2988,7 +2988,7 @@ static uint64_t watch_mem_read(void *opaque, target_phys_addr_t addr,
}
}
static void watch_mem_write(void *opaque, target_phys_addr_t addr,
static void watch_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_WRITE);
@ -3012,7 +3012,7 @@ static const MemoryRegionOps watch_mem_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static uint64_t subpage_read(void *opaque, target_phys_addr_t addr,
static uint64_t subpage_read(void *opaque, hwaddr addr,
unsigned len)
{
subpage_t *mmio = opaque;
@ -3030,7 +3030,7 @@ static uint64_t subpage_read(void *opaque, target_phys_addr_t addr,
return io_mem_read(section->mr, addr, len);
}
static void subpage_write(void *opaque, target_phys_addr_t addr,
static void subpage_write(void *opaque, hwaddr addr,
uint64_t value, unsigned len)
{
subpage_t *mmio = opaque;
@ -3055,7 +3055,7 @@ static const MemoryRegionOps subpage_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static uint64_t subpage_ram_read(void *opaque, target_phys_addr_t addr,
static uint64_t subpage_ram_read(void *opaque, hwaddr addr,
unsigned size)
{
ram_addr_t raddr = addr;
@ -3068,7 +3068,7 @@ static uint64_t subpage_ram_read(void *opaque, target_phys_addr_t addr,
}
}
static void subpage_ram_write(void *opaque, target_phys_addr_t addr,
static void subpage_ram_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
ram_addr_t raddr = addr;
@ -3112,7 +3112,7 @@ static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
return 0;
}
static subpage_t *subpage_init(target_phys_addr_t base)
static subpage_t *subpage_init(hwaddr base)
{
subpage_t *mmio;
@ -3143,7 +3143,7 @@ static uint16_t dummy_section(MemoryRegion *mr)
return phys_section_add(&section);
}
MemoryRegion *iotlb_to_region(target_phys_addr_t index)
MemoryRegion *iotlb_to_region(hwaddr index)
{
return phys_sections[index & ~TARGET_PAGE_MASK].mr;
}
@ -3333,8 +3333,8 @@ int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
#else
static void invalidate_and_set_dirty(target_phys_addr_t addr,
target_phys_addr_t length)
static void invalidate_and_set_dirty(hwaddr addr,
hwaddr length)
{
if (!cpu_physical_memory_is_dirty(addr)) {
/* invalidate code */
@ -3345,14 +3345,14 @@ static void invalidate_and_set_dirty(target_phys_addr_t addr,
xen_modified_memory(addr, length);
}
void address_space_rw(AddressSpace *as, target_phys_addr_t addr, uint8_t *buf,
void address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf,
int len, bool is_write)
{
AddressSpaceDispatch *d = as->dispatch;
int l;
uint8_t *ptr;
uint32_t val;
target_phys_addr_t page;
hwaddr page;
MemoryRegionSection *section;
while (len > 0) {
@ -3364,7 +3364,7 @@ void address_space_rw(AddressSpace *as, target_phys_addr_t addr, uint8_t *buf,
if (is_write) {
if (!memory_region_is_ram(section->mr)) {
target_phys_addr_t addr1;
hwaddr addr1;
addr1 = memory_region_section_addr(section, addr);
/* XXX: could force cpu_single_env to NULL to avoid
potential bugs */
@ -3397,7 +3397,7 @@ void address_space_rw(AddressSpace *as, target_phys_addr_t addr, uint8_t *buf,
} else {
if (!(memory_region_is_ram(section->mr) ||
memory_region_is_romd(section->mr))) {
target_phys_addr_t addr1;
hwaddr addr1;
/* I/O case */
addr1 = memory_region_section_addr(section, addr);
if (l >= 4 && ((addr1 & 3) == 0)) {
@ -3431,7 +3431,7 @@ void address_space_rw(AddressSpace *as, target_phys_addr_t addr, uint8_t *buf,
}
}
void address_space_write(AddressSpace *as, target_phys_addr_t addr,
void address_space_write(AddressSpace *as, hwaddr addr,
const uint8_t *buf, int len)
{
address_space_rw(as, addr, (uint8_t *)buf, len, true);
@ -3444,26 +3444,26 @@ void address_space_write(AddressSpace *as, target_phys_addr_t addr,
* @addr: address within that address space
* @buf: buffer with the data transferred
*/
void address_space_read(AddressSpace *as, target_phys_addr_t addr, uint8_t *buf, int len)
void address_space_read(AddressSpace *as, hwaddr addr, uint8_t *buf, int len)
{
address_space_rw(as, addr, buf, len, false);
}
void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
int len, int is_write)
{
return address_space_rw(&address_space_memory, addr, buf, len, is_write);
}
/* used for ROM loading : can write in RAM and ROM */
void cpu_physical_memory_write_rom(target_phys_addr_t addr,
void cpu_physical_memory_write_rom(hwaddr addr,
const uint8_t *buf, int len)
{
AddressSpaceDispatch *d = address_space_memory.dispatch;
int l;
uint8_t *ptr;
target_phys_addr_t page;
hwaddr page;
MemoryRegionSection *section;
while (len > 0) {
@ -3494,8 +3494,8 @@ void cpu_physical_memory_write_rom(target_phys_addr_t addr,
typedef struct {
void *buffer;
target_phys_addr_t addr;
target_phys_addr_t len;
hwaddr addr;
hwaddr len;
} BounceBuffer;
static BounceBuffer bounce;
@ -3546,15 +3546,15 @@ static void cpu_notify_map_clients(void)
* likely to succeed.
*/
void *address_space_map(AddressSpace *as,
target_phys_addr_t addr,
target_phys_addr_t *plen,
hwaddr addr,
hwaddr *plen,
bool is_write)
{
AddressSpaceDispatch *d = as->dispatch;
target_phys_addr_t len = *plen;
target_phys_addr_t todo = 0;
hwaddr len = *plen;
hwaddr todo = 0;
int l;
target_phys_addr_t page;
hwaddr page;
MemoryRegionSection *section;
ram_addr_t raddr = RAM_ADDR_MAX;
ram_addr_t rlen;
@ -3600,8 +3600,8 @@ void *address_space_map(AddressSpace *as,
* Will also mark the memory as dirty if is_write == 1. access_len gives
* the amount of memory that was actually read or written by the caller.
*/
void address_space_unmap(AddressSpace *as, void *buffer, target_phys_addr_t len,
int is_write, target_phys_addr_t access_len)
void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
int is_write, hwaddr access_len)
{
if (buffer != bounce.buffer) {
if (is_write) {
@ -3629,21 +3629,21 @@ void address_space_unmap(AddressSpace *as, void *buffer, target_phys_addr_t len,
cpu_notify_map_clients();
}
void *cpu_physical_memory_map(target_phys_addr_t addr,
target_phys_addr_t *plen,
void *cpu_physical_memory_map(hwaddr addr,
hwaddr *plen,
int is_write)
{
return address_space_map(&address_space_memory, addr, plen, is_write);
}
void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
int is_write, target_phys_addr_t access_len)
void cpu_physical_memory_unmap(void *buffer, hwaddr len,
int is_write, hwaddr access_len)
{
return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len);
}
/* warning: addr must be aligned */
static inline uint32_t ldl_phys_internal(target_phys_addr_t addr,
static inline uint32_t ldl_phys_internal(hwaddr addr,
enum device_endian endian)
{
uint8_t *ptr;
@ -3686,23 +3686,23 @@ static inline uint32_t ldl_phys_internal(target_phys_addr_t addr,
return val;
}
uint32_t ldl_phys(target_phys_addr_t addr)
uint32_t ldl_phys(hwaddr addr)
{
return ldl_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
}
uint32_t ldl_le_phys(target_phys_addr_t addr)
uint32_t ldl_le_phys(hwaddr addr)
{
return ldl_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
}
uint32_t ldl_be_phys(target_phys_addr_t addr)
uint32_t ldl_be_phys(hwaddr addr)
{
return ldl_phys_internal(addr, DEVICE_BIG_ENDIAN);
}
/* warning: addr must be aligned */
static inline uint64_t ldq_phys_internal(target_phys_addr_t addr,
static inline uint64_t ldq_phys_internal(hwaddr addr,
enum device_endian endian)
{
uint8_t *ptr;
@ -3745,23 +3745,23 @@ static inline uint64_t ldq_phys_internal(target_phys_addr_t addr,
return val;
}
uint64_t ldq_phys(target_phys_addr_t addr)
uint64_t ldq_phys(hwaddr addr)
{
return ldq_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
}
uint64_t ldq_le_phys(target_phys_addr_t addr)
uint64_t ldq_le_phys(hwaddr addr)
{
return ldq_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
}
uint64_t ldq_be_phys(target_phys_addr_t addr)
uint64_t ldq_be_phys(hwaddr addr)
{
return ldq_phys_internal(addr, DEVICE_BIG_ENDIAN);
}
/* XXX: optimize */
uint32_t ldub_phys(target_phys_addr_t addr)
uint32_t ldub_phys(hwaddr addr)
{
uint8_t val;
cpu_physical_memory_read(addr, &val, 1);
@ -3769,7 +3769,7 @@ uint32_t ldub_phys(target_phys_addr_t addr)
}
/* warning: addr must be aligned */
static inline uint32_t lduw_phys_internal(target_phys_addr_t addr,
static inline uint32_t lduw_phys_internal(hwaddr addr,
enum device_endian endian)
{
uint8_t *ptr;
@ -3812,17 +3812,17 @@ static inline uint32_t lduw_phys_internal(target_phys_addr_t addr,
return val;
}
uint32_t lduw_phys(target_phys_addr_t addr)
uint32_t lduw_phys(hwaddr addr)
{
return lduw_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
}
uint32_t lduw_le_phys(target_phys_addr_t addr)
uint32_t lduw_le_phys(hwaddr addr)
{
return lduw_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
}
uint32_t lduw_be_phys(target_phys_addr_t addr)
uint32_t lduw_be_phys(hwaddr addr)
{
return lduw_phys_internal(addr, DEVICE_BIG_ENDIAN);
}
@ -3830,7 +3830,7 @@ uint32_t lduw_be_phys(target_phys_addr_t addr)
/* warning: addr must be aligned. The ram page is not masked as dirty
and the code inside is not invalidated. It is useful if the dirty
bits are used to track modified PTEs */
void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val)
void stl_phys_notdirty(hwaddr addr, uint32_t val)
{
uint8_t *ptr;
MemoryRegionSection *section;
@ -3862,7 +3862,7 @@ void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val)
}
}
void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val)
void stq_phys_notdirty(hwaddr addr, uint64_t val)
{
uint8_t *ptr;
MemoryRegionSection *section;
@ -3890,7 +3890,7 @@ void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val)
}
/* warning: addr must be aligned */
static inline void stl_phys_internal(target_phys_addr_t addr, uint32_t val,
static inline void stl_phys_internal(hwaddr addr, uint32_t val,
enum device_endian endian)
{
uint8_t *ptr;
@ -3934,30 +3934,30 @@ static inline void stl_phys_internal(target_phys_addr_t addr, uint32_t val,
}
}
void stl_phys(target_phys_addr_t addr, uint32_t val)
void stl_phys(hwaddr addr, uint32_t val)
{
stl_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN);
}
void stl_le_phys(target_phys_addr_t addr, uint32_t val)
void stl_le_phys(hwaddr addr, uint32_t val)
{
stl_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN);
}
void stl_be_phys(target_phys_addr_t addr, uint32_t val)
void stl_be_phys(hwaddr addr, uint32_t val)
{
stl_phys_internal(addr, val, DEVICE_BIG_ENDIAN);
}
/* XXX: optimize */
void stb_phys(target_phys_addr_t addr, uint32_t val)
void stb_phys(hwaddr addr, uint32_t val)
{
uint8_t v = val;
cpu_physical_memory_write(addr, &v, 1);
}
/* warning: addr must be aligned */
static inline void stw_phys_internal(target_phys_addr_t addr, uint32_t val,
static inline void stw_phys_internal(hwaddr addr, uint32_t val,
enum device_endian endian)
{
uint8_t *ptr;
@ -4001,35 +4001,35 @@ static inline void stw_phys_internal(target_phys_addr_t addr, uint32_t val,
}
}
void stw_phys(target_phys_addr_t addr, uint32_t val)
void stw_phys(hwaddr addr, uint32_t val)
{
stw_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN);
}
void stw_le_phys(target_phys_addr_t addr, uint32_t val)
void stw_le_phys(hwaddr addr, uint32_t val)
{
stw_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN);
}
void stw_be_phys(target_phys_addr_t addr, uint32_t val)
void stw_be_phys(hwaddr addr, uint32_t val)
{
stw_phys_internal(addr, val, DEVICE_BIG_ENDIAN);
}
/* XXX: optimize */
void stq_phys(target_phys_addr_t addr, uint64_t val)
void stq_phys(hwaddr addr, uint64_t val)
{
val = tswap64(val);
cpu_physical_memory_write(addr, &val, 8);
}
void stq_le_phys(target_phys_addr_t addr, uint64_t val)
void stq_le_phys(hwaddr addr, uint64_t val)
{
val = cpu_to_le64(val);
cpu_physical_memory_write(addr, &val, 8);
}
void stq_be_phys(target_phys_addr_t addr, uint64_t val)
void stq_be_phys(hwaddr addr, uint64_t val)
{
val = cpu_to_be64(val);
cpu_physical_memory_write(addr, &val, 8);
@ -4040,7 +4040,7 @@ int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
uint8_t *buf, int len, int is_write)
{
int l;
target_phys_addr_t phys_addr;
hwaddr phys_addr;
target_ulong page;
while (len > 0) {
@ -4195,7 +4195,7 @@ bool virtio_is_big_endian(void)
#endif
#ifndef CONFIG_USER_ONLY
bool cpu_physical_memory_is_io(target_phys_addr_t phys_addr)
bool cpu_physical_memory_is_io(hwaddr phys_addr)
{
MemoryRegionSection *section;

4
hw/a9mpcore.c
View File

@ -26,7 +26,7 @@ typedef struct a9mp_priv_state {
uint32_t num_irq;
} a9mp_priv_state;
static uint64_t a9_scu_read(void *opaque, target_phys_addr_t offset,
static uint64_t a9_scu_read(void *opaque, hwaddr offset,
unsigned size)
{
a9mp_priv_state *s = (a9mp_priv_state *)opaque;
@ -57,7 +57,7 @@ static uint64_t a9_scu_read(void *opaque, target_phys_addr_t offset,
}
}
static void a9_scu_write(void *opaque, target_phys_addr_t offset,
static void a9_scu_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
a9mp_priv_state *s = (a9mp_priv_state *)opaque;

12
hw/alpha_pci.c
View File

@ -15,7 +15,7 @@
/* PCI IO reads/writes, to byte-word addressable memory. */
/* ??? Doesn't handle multiple PCI busses. */
static uint64_t bw_io_read(void *opaque, target_phys_addr_t addr, unsigned size)
static uint64_t bw_io_read(void *opaque, hwaddr addr, unsigned size)
{
switch (size) {
case 1:
@ -28,7 +28,7 @@ static uint64_t bw_io_read(void *opaque, target_phys_addr_t addr, unsigned size)
abort();
}
static void bw_io_write(void *opaque, target_phys_addr_t addr,
static void bw_io_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
switch (size) {
@ -57,14 +57,14 @@ const MemoryRegionOps alpha_pci_bw_io_ops = {
};
/* PCI config space reads/writes, to byte-word addressable memory. */
static uint64_t bw_conf1_read(void *opaque, target_phys_addr_t addr,
static uint64_t bw_conf1_read(void *opaque, hwaddr addr,
unsigned size)
{
PCIBus *b = opaque;
return pci_data_read(b, addr, size);
}
static void bw_conf1_write(void *opaque, target_phys_addr_t addr,
static void bw_conf1_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
PCIBus *b = opaque;
@ -83,12 +83,12 @@ const MemoryRegionOps alpha_pci_conf1_ops = {
/* PCI/EISA Interrupt Acknowledge Cycle. */
static uint64_t iack_read(void *opaque, target_phys_addr_t addr, unsigned size)
static uint64_t iack_read(void *opaque, hwaddr addr, unsigned size)
{
return pic_read_irq(isa_pic);
}
static void special_write(void *opaque, target_phys_addr_t addr,
static void special_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
qemu_log("pci: special write cycle");

12
hw/alpha_typhoon.c
View File

@ -70,7 +70,7 @@ static void cpu_irq_change(CPUAlphaState *env, uint64_t req)
}
}
static uint64_t cchip_read(void *opaque, target_phys_addr_t addr, unsigned size)
static uint64_t cchip_read(void *opaque, hwaddr addr, unsigned size)
{
CPUAlphaState *env = cpu_single_env;
TyphoonState *s = opaque;
@ -203,13 +203,13 @@ static uint64_t cchip_read(void *opaque, target_phys_addr_t addr, unsigned size)
return ret;
}
static uint64_t dchip_read(void *opaque, target_phys_addr_t addr, unsigned size)
static uint64_t dchip_read(void *opaque, hwaddr addr, unsigned size)
{
/* Skip this. It's all related to DRAM timing and setup. */
return 0;
}
static uint64_t pchip_read(void *opaque, target_phys_addr_t addr, unsigned size)
static uint64_t pchip_read(void *opaque, hwaddr addr, unsigned size)
{
TyphoonState *s = opaque;
uint64_t ret = 0;
@ -306,7 +306,7 @@ static uint64_t pchip_read(void *opaque, target_phys_addr_t addr, unsigned size)
return ret;
}
static void cchip_write(void *opaque, target_phys_addr_t addr,
static void cchip_write(void *opaque, hwaddr addr,
uint64_t v32, unsigned size)
{
TyphoonState *s = opaque;
@ -463,13 +463,13 @@ static void cchip_write(void *opaque, target_phys_addr_t addr,
}
}
static void dchip_write(void *opaque, target_phys_addr_t addr,
static void dchip_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
/* Skip this. It's all related to DRAM timing and setup. */
}
static void pchip_write(void *opaque, target_phys_addr_t addr,
static void pchip_write(void *opaque, hwaddr addr,
uint64_t v32, unsigned size)
{
TyphoonState *s = opaque;

2
hw/an5206.c
View File

@ -27,7 +27,7 @@ static void an5206_init(QEMUMachineInitArgs *args)
CPUM68KState *env;
int kernel_size;
uint64_t elf_entry;
target_phys_addr_t entry;
hwaddr entry;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *sram = g_new(MemoryRegion, 1);

24
hw/apb_pci.c
View File

@ -87,7 +87,7 @@ typedef struct APBState {
static void pci_apb_set_irq(void *opaque, int irq_num, int level);
static void apb_config_writel (void *opaque, target_phys_addr_t addr,
static void apb_config_writel (void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
APBState *s = opaque;
@ -152,7 +152,7 @@ static void apb_config_writel (void *opaque, target_phys_addr_t addr,
}
static uint64_t apb_config_readl (void *opaque,
target_phys_addr_t addr, unsigned size)
hwaddr addr, unsigned size)
{
APBState *s = opaque;
uint32_t val;
@ -212,7 +212,7 @@ static const MemoryRegionOps apb_config_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void apb_pci_config_write(void *opaque, target_phys_addr_t addr,
static void apb_pci_config_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
APBState *s = opaque;
@ -222,7 +222,7 @@ static void apb_pci_config_write(void *opaque, target_phys_addr_t addr,
pci_data_write(s->bus, addr, val, size);
}
static uint64_t apb_pci_config_read(void *opaque, target_phys_addr_t addr,
static uint64_t apb_pci_config_read(void *opaque, hwaddr addr,
unsigned size)
{
uint32_t ret;
@ -234,25 +234,25 @@ static uint64_t apb_pci_config_read(void *opaque, target_phys_addr_t addr,
return ret;
}
static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
static void pci_apb_iowriteb (void *opaque, hwaddr addr,
uint32_t val)
{
cpu_outb(addr & IOPORTS_MASK, val);
}
static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
static void pci_apb_iowritew (void *opaque, hwaddr addr,
uint32_t val)
{
cpu_outw(addr & IOPORTS_MASK, bswap16(val));
}
static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
static void pci_apb_iowritel (void *opaque, hwaddr addr,
uint32_t val)
{
cpu_outl(addr & IOPORTS_MASK, bswap32(val));
}
static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
static uint32_t pci_apb_ioreadb (void *opaque, hwaddr addr)
{
uint32_t val;
@ -260,7 +260,7 @@ static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
return val;
}
static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
static uint32_t pci_apb_ioreadw (void *opaque, hwaddr addr)
{
uint32_t val;
@ -268,7 +268,7 @@ static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
return val;
}
static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
static uint32_t pci_apb_ioreadl (void *opaque, hwaddr addr)
{
uint32_t val;
@ -351,8 +351,8 @@ static int apb_pci_bridge_initfn(PCIDevice *dev)
return 0;
}
PCIBus *pci_apb_init(target_phys_addr_t special_base,
target_phys_addr_t mem_base,
PCIBus *pci_apb_init(hwaddr special_base,
hwaddr mem_base,
qemu_irq *ivec_irqs, PCIBus **bus2, PCIBus **bus3,
qemu_irq **pbm_irqs)
{

4
hw/apb_pci.h
View File

@ -3,8 +3,8 @@
#include "qemu-common.h"
PCIBus *pci_apb_init(target_phys_addr_t special_base,
target_phys_addr_t mem_base,
PCIBus *pci_apb_init(hwaddr special_base,
hwaddr mem_base,
qemu_irq *ivec_irqs, PCIBus **bus2, PCIBus **bus3,
qemu_irq **pbm_irqs);
#endif

14
hw/apic.c
View File

@ -630,25 +630,25 @@ static void apic_timer(void *opaque)
apic_timer_update(s, s->next_time);
}
static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
static uint32_t apic_mem_readb(void *opaque, hwaddr addr)
{
return 0;
}
static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
static uint32_t apic_mem_readw(void *opaque, hwaddr addr)
{
return 0;
}
static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
static void apic_mem_writeb(void *opaque, hwaddr addr, uint32_t val)
{
}
static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
static void apic_mem_writew(void *opaque, hwaddr addr, uint32_t val)
{
}
static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
static uint32_t apic_mem_readl(void *opaque, hwaddr addr)
{
DeviceState *d;
APICCommonState *s;
@ -732,7 +732,7 @@ static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
return val;
}
static void apic_send_msi(target_phys_addr_t addr, uint32_t data)
static void apic_send_msi(hwaddr addr, uint32_t data)
{
uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
@ -743,7 +743,7 @@ static void apic_send_msi(target_phys_addr_t addr, uint32_t data)
apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode);
}
static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
static void apic_mem_writel(void *opaque, hwaddr addr, uint32_t val)
{
DeviceState *d;
APICCommonState *s;

2
hw/apic_common.c
View File

@ -89,7 +89,7 @@ void apic_enable_tpr_access_reporting(DeviceState *d, bool enable)
}
}
void apic_enable_vapic(DeviceState *d, target_phys_addr_t paddr)
void apic_enable_vapic(DeviceState *d, hwaddr paddr)
{
APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
APICCommonClass *info = APIC_COMMON_GET_CLASS(s);

4
hw/apic_internal.h
View File

@ -124,7 +124,7 @@ struct APICCommonState {
uint32_t vapic_control;
DeviceState *vapic;
target_phys_addr_t vapic_paddr; /* note: persistence via kvmvapic */
hwaddr vapic_paddr; /* note: persistence via kvmvapic */
};
typedef struct VAPICState {
@ -140,7 +140,7 @@ extern bool apic_report_tpr_access;
void apic_report_irq_delivered(int delivered);
bool apic_next_timer(APICCommonState *s, int64_t current_time);
void apic_enable_tpr_access_reporting(DeviceState *d, bool enable);
void apic_enable_vapic(DeviceState *d, target_phys_addr_t paddr);
void apic_enable_vapic(DeviceState *d, hwaddr paddr);
void vapic_report_tpr_access(DeviceState *dev, void *cpu, target_ulong ip,
TPRAccess access);

12
hw/arm-misc.h
View File

@ -30,15 +30,15 @@ struct arm_boot_info {
const char *kernel_cmdline;
const char *initrd_filename;
const char *dtb_filename;
target_phys_addr_t loader_start;
hwaddr loader_start;
/* multicore boards that use the default secondary core boot functions
* need to put the address of the secondary boot code, the boot reg,
* and the GIC address in the next 3 values, respectively. boards that
* have their own boot functions can use these values as they want.
*/
target_phys_addr_t smp_loader_start;
target_phys_addr_t smp_bootreg_addr;
target_phys_addr_t gic_cpu_if_addr;
hwaddr smp_loader_start;
hwaddr smp_bootreg_addr;
hwaddr gic_cpu_if_addr;
int nb_cpus;
int board_id;
int (*atag_board)(const struct arm_boot_info *info, void *p);
@ -56,8 +56,8 @@ struct arm_boot_info {
const struct arm_boot_info *info);
/* Used internally by arm_boot.c */
int is_linux;
target_phys_addr_t initrd_size;
target_phys_addr_t entry;
hwaddr initrd_size;
hwaddr entry;
};
void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info);

8
hw/arm11mpcore.c
View File

@ -27,7 +27,7 @@ typedef struct mpcore_priv_state {
/* Per-CPU private memory mapped IO. */
static uint64_t mpcore_scu_read(void *opaque, target_phys_addr_t offset,
static uint64_t mpcore_scu_read(void *opaque, hwaddr offset,
unsigned size)
{
mpcore_priv_state *s = (mpcore_priv_state *)opaque;
@ -48,7 +48,7 @@ static uint64_t mpcore_scu_read(void *opaque, target_phys_addr_t offset,
}
}
static void mpcore_scu_write(void *opaque, target_phys_addr_t offset,
static void mpcore_scu_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
mpcore_priv_state *s = (mpcore_priv_state *)opaque;
@ -89,7 +89,7 @@ static void mpcore_priv_map_setup(mpcore_priv_state *s)
* at 0x200, 0x300...
*/
for (i = 0; i < (s->num_cpu + 1); i++) {
target_phys_addr_t offset = 0x100 + (i * 0x100);
hwaddr offset = 0x100 + (i * 0x100);
memory_region_add_subregion(&s->container, offset,
sysbus_mmio_get_region(gicbusdev, i + 1));
}
@ -98,7 +98,7 @@ static void mpcore_priv_map_setup(mpcore_priv_state *s)
*/
for (i = 0; i < (s->num_cpu + 1) * 2; i++) {
/* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */
target_phys_addr_t offset = 0x600 + (i >> 1) * 0x100 + (i & 1) * 0x20;
hwaddr offset = 0x600 + (i >> 1) * 0x100 + (i & 1) * 0x20;
memory_region_add_subregion(&s->container, offset,
sysbus_mmio_get_region(busdev, i));
}

14
hw/arm_boot.c
View File

@ -89,8 +89,8 @@ static void default_reset_secondary(ARMCPU *cpu,
static void set_kernel_args(const struct arm_boot_info *info)
{
int initrd_size = info->initrd_size;
target_phys_addr_t base = info->loader_start;
target_phys_addr_t p;
hwaddr base = info->loader_start;
hwaddr p;
p = base + KERNEL_ARGS_ADDR;
/* ATAG_CORE */
@ -142,10 +142,10 @@ static void set_kernel_args(const struct arm_boot_info *info)
static void set_kernel_args_old(const struct arm_boot_info *info)
{
target_phys_addr_t p;
hwaddr p;
const char *s;
int initrd_size = info->initrd_size;
target_phys_addr_t base = info->loader_start;
hwaddr base = info->loader_start;
/* see linux/include/asm-arm/setup.h */
p = base + KERNEL_ARGS_ADDR;
@ -213,7 +213,7 @@ static void set_kernel_args_old(const struct arm_boot_info *info)
}
}
static int load_dtb(target_phys_addr_t addr, const struct arm_boot_info *binfo)
static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo)
{
#ifdef CONFIG_FDT
uint32_t *mem_reg_property;
@ -342,7 +342,7 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
int n;
int is_linux = 0;
uint64_t elf_entry;
target_phys_addr_t entry;
hwaddr entry;
int big_endian;
QemuOpts *machine_opts;
@ -419,7 +419,7 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
*/
if (info->dtb_filename) {
/* Place the DTB after the initrd in memory */
target_phys_addr_t dtb_start = TARGET_PAGE_ALIGN(info->loader_start
hwaddr dtb_start = TARGET_PAGE_ALIGN(info->loader_start
+ INITRD_LOAD_ADDR
+ initrd_size);
if (load_dtb(dtb_start, info)) {

20
hw/arm_gic.c
View File

@ -212,7 +212,7 @@ void gic_complete_irq(GICState *s, int cpu, int irq)
}
}
static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
static uint32_t gic_dist_readb(void *opaque, hwaddr offset)
{
GICState *s = (GICState *)opaque;
uint32_t res;
@ -328,7 +328,7 @@ bad_reg:
return 0;
}
static uint32_t gic_dist_readw(void *opaque, target_phys_addr_t offset)
static uint32_t gic_dist_readw(void *opaque, hwaddr offset)
{
uint32_t val;
val = gic_dist_readb(opaque, offset);
@ -336,7 +336,7 @@ static uint32_t gic_dist_readw(void *opaque, target_phys_addr_t offset)
return val;
}
static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
static uint32_t gic_dist_readl(void *opaque, hwaddr offset)
{
uint32_t val;
val = gic_dist_readw(opaque, offset);
@ -344,7 +344,7 @@ static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
return val;
}
static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
static void gic_dist_writeb(void *opaque, hwaddr offset,
uint32_t value)
{
GICState *s = (GICState *)opaque;
@ -490,14 +490,14 @@ bad_reg:
hw_error("gic_dist_writeb: Bad offset %x\n", (int)offset);
}
static void gic_dist_writew(void *opaque, target_phys_addr_t offset,
static void gic_dist_writew(void *opaque, hwaddr offset,
uint32_t value)
{
gic_dist_writeb(opaque, offset, value & 0xff);
gic_dist_writeb(opaque, offset + 1, value >> 8);
}
static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
static void gic_dist_writel(void *opaque, hwaddr offset,
uint32_t value)
{
GICState *s = (GICState *)opaque;
@ -584,14 +584,14 @@ static void gic_cpu_write(GICState *s, int cpu, int offset, uint32_t value)
}
/* Wrappers to read/write the GIC CPU interface for the current CPU */
static uint64_t gic_thiscpu_read(void *opaque, target_phys_addr_t addr,
static uint64_t gic_thiscpu_read(void *opaque, hwaddr addr,
unsigned size)
{
GICState *s = (GICState *)opaque;
return gic_cpu_read(s, gic_get_current_cpu(s), addr);
}
static void gic_thiscpu_write(void *opaque, target_phys_addr_t addr,
static void gic_thiscpu_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
GICState *s = (GICState *)opaque;
@ -601,7 +601,7 @@ static void gic_thiscpu_write(void *opaque, target_phys_addr_t addr,
/* Wrappers to read/write the GIC CPU interface for a specific CPU.
* These just decode the opaque pointer into GICState* + cpu id.
*/
static uint64_t gic_do_cpu_read(void *opaque, target_phys_addr_t addr,
static uint64_t gic_do_cpu_read(void *opaque, hwaddr addr,
unsigned size)
{
GICState **backref = (GICState **)opaque;
@ -610,7 +610,7 @@ static uint64_t gic_do_cpu_read(void *opaque, target_phys_addr_t addr,
return gic_cpu_read(s, id, addr);
}
static void gic_do_cpu_write(void *opaque, target_phys_addr_t addr,
static void gic_do_cpu_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
GICState **backref = (GICState **)opaque;

4
hw/arm_l2x0.c
View File

@ -51,7 +51,7 @@ static const VMStateDescription vmstate_l2x0 = {
};
static uint64_t l2x0_priv_read(void *opaque, target_phys_addr_t offset,
static uint64_t l2x0_priv_read(void *opaque, hwaddr offset,
unsigned size)
{
uint32_t cache_data;
@ -93,7 +93,7 @@ static uint64_t l2x0_priv_read(void *opaque, target_phys_addr_t offset,
return 0;
}
static void l2x0_priv_write(void *opaque, target_phys_addr_t offset,
static void l2x0_priv_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
l2x0_state *s = (l2x0_state *)opaque;

12
hw/arm_mptimer.c
View File

@ -92,7 +92,7 @@ static void timerblock_tick(void *opaque)
timerblock_update_irq(tb);
}
static uint64_t timerblock_read(void *opaque, target_phys_addr_t addr,
static uint64_t timerblock_read(void *opaque, hwaddr addr,
unsigned size)
{
timerblock *tb = (timerblock *)opaque;
@ -120,7 +120,7 @@ static uint64_t timerblock_read(void *opaque, target_phys_addr_t addr,
}
}
static void timerblock_write(void *opaque, target_phys_addr_t addr,
static void timerblock_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
timerblock *tb = (timerblock *)opaque;
@ -159,7 +159,7 @@ static void timerblock_write(void *opaque, target_phys_addr_t addr,
/* Wrapper functions to implement the "read timer/watchdog for
* the current CPU" memory regions.
*/
static uint64_t arm_thistimer_read(void *opaque, target_phys_addr_t addr,
static uint64_t arm_thistimer_read(void *opaque, hwaddr addr,
unsigned size)
{
arm_mptimer_state *s = (arm_mptimer_state *)opaque;
@ -167,7 +167,7 @@ static uint64_t arm_thistimer_read(void *opaque, target_phys_addr_t addr,
return timerblock_read(&s->timerblock[id * 2], addr, size);
}
static void arm_thistimer_write(void *opaque, target_phys_addr_t addr,
static void arm_thistimer_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
arm_mptimer_state *s = (arm_mptimer_state *)opaque;
@ -175,7 +175,7 @@ static void arm_thistimer_write(void *opaque, target_phys_addr_t addr,
timerblock_write(&s->timerblock[id * 2], addr, value, size);
}
static uint64_t arm_thiswdog_read(void *opaque, target_phys_addr_t addr,
static uint64_t arm_thiswdog_read(void *opaque, hwaddr addr,
unsigned size)
{
arm_mptimer_state *s = (arm_mptimer_state *)opaque;
@ -183,7 +183,7 @@ static uint64_t arm_thiswdog_read(void *opaque, target_phys_addr_t addr,
return timerblock_read(&s->timerblock[id * 2 + 1], addr, size);
}
static void arm_thiswdog_write(void *opaque, target_phys_addr_t addr,
static void arm_thiswdog_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
arm_mptimer_state *s = (arm_mptimer_state *)opaque;

4
hw/arm_sysctl.c
View File

@ -92,7 +92,7 @@ static void arm_sysctl_reset(DeviceState *d)
}
}
static uint64_t arm_sysctl_read(void *opaque, target_phys_addr_t offset,
static uint64_t arm_sysctl_read(void *opaque, hwaddr offset,
unsigned size)
{
arm_sysctl_state *s = (arm_sysctl_state *)opaque;
@ -189,7 +189,7 @@ static uint64_t arm_sysctl_read(void *opaque, target_phys_addr_t offset,
}
}
static void arm_sysctl_write(void *opaque, target_phys_addr_t offset,
static void arm_sysctl_write(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
arm_sysctl_state *s = (arm_sysctl_state *)opaque;

12
hw/arm_timer.c
View File

@ -45,7 +45,7 @@ static void arm_timer_update(arm_timer_state *s)
}
}
static uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
static uint32_t arm_timer_read(void *opaque, hwaddr offset)
{
arm_timer_state *s = (arm_timer_state *)opaque;
@ -87,7 +87,7 @@ static void arm_timer_recalibrate(arm_timer_state *s, int reload)
ptimer_set_limit(s->timer, limit, reload);
}
static void arm_timer_write(void *opaque, target_phys_addr_t offset,
static void arm_timer_write(void *opaque, hwaddr offset,
uint32_t value)
{
arm_timer_state *s = (arm_timer_state *)opaque;
@ -202,7 +202,7 @@ static void sp804_set_irq(void *opaque, int irq, int level)
qemu_set_irq(s->irq, s->level[0] || s->level[1]);
}
static uint64_t sp804_read(void *opaque, target_phys_addr_t offset,
static uint64_t sp804_read(void *opaque, hwaddr offset,
unsigned size)
{
sp804_state *s = (sp804_state *)opaque;
@ -230,7 +230,7 @@ static uint64_t sp804_read(void *opaque, target_phys_addr_t offset,
return 0;
}
static void sp804_write(void *opaque, target_phys_addr_t offset,
static void sp804_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
sp804_state *s = (sp804_state *)opaque;
@ -291,7 +291,7 @@ typedef struct {
arm_timer_state *timer[3];
} icp_pit_state;
static uint64_t icp_pit_read(void *opaque, target_phys_addr_t offset,
static uint64_t icp_pit_read(void *opaque, hwaddr offset,
unsigned size)
{
icp_pit_state *s = (icp_pit_state *)opaque;
@ -306,7 +306,7 @@ static uint64_t icp_pit_read(void *opaque, target_phys_addr_t offset,
return arm_timer_read(s->timer[n], offset & 0xff);
}
static void icp_pit_write(void *opaque, target_phys_addr_t offset,
static void icp_pit_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
icp_pit_state *s = (icp_pit_state *)opaque;

12
hw/armv7m.c
View File

@ -25,14 +25,14 @@ static inline uint32_t bitband_addr(void * opaque, uint32_t addr)
}
static uint32_t bitband_readb(void *opaque, target_phys_addr_t offset)
static uint32_t bitband_readb(void *opaque, hwaddr offset)
{
uint8_t v;
cpu_physical_memory_read(bitband_addr(opaque, offset), &v, 1);
return (v & (1 << ((offset >> 2) & 7))) != 0;
}
static void bitband_writeb(void *opaque, target_phys_addr_t offset,
static void bitband_writeb(void *opaque, hwaddr offset,
uint32_t value)
{
uint32_t addr;
@ -48,7 +48,7 @@ static void bitband_writeb(void *opaque, target_phys_addr_t offset,
cpu_physical_memory_write(addr, &v, 1);
}
static uint32_t bitband_readw(void *opaque, target_phys_addr_t offset)
static uint32_t bitband_readw(void *opaque, hwaddr offset)
{
uint32_t addr;
uint16_t mask;
@ -60,7 +60,7 @@ static uint32_t bitband_readw(void *opaque, target_phys_addr_t offset)
return (v & mask) != 0;
}
static void bitband_writew(void *opaque, target_phys_addr_t offset,
static void bitband_writew(void *opaque, hwaddr offset,
uint32_t value)
{
uint32_t addr;
@ -77,7 +77,7 @@ static void bitband_writew(void *opaque, target_phys_addr_t offset,
cpu_physical_memory_write(addr, (uint8_t *)&v, 2);
}
static uint32_t bitband_readl(void *opaque, target_phys_addr_t offset)
static uint32_t bitband_readl(void *opaque, hwaddr offset)
{
uint32_t addr;
uint32_t mask;
@ -89,7 +89,7 @@ static uint32_t bitband_readl(void *opaque, target_phys_addr_t offset)
return (v & mask) != 0;
}
static void bitband_writel(void *opaque, target_phys_addr_t offset,
static void bitband_writel(void *opaque, hwaddr offset,
uint32_t value)
{
uint32_t addr;

4
hw/armv7m_nvic.c
View File

@ -392,7 +392,7 @@ static void nvic_writel(void *opaque, uint32_t offset, uint32_t value)
}
}
static uint64_t nvic_sysreg_read(void *opaque, target_phys_addr_t addr,
static uint64_t nvic_sysreg_read(void *opaque, hwaddr addr,
unsigned size)
{
/* At the moment we only support the ID registers for byte/word access.
@ -412,7 +412,7 @@ static uint64_t nvic_sysreg_read(void *opaque, target_phys_addr_t addr,
hw_error("NVIC: Bad read of size %d at offset 0x%x\n", size, offset);
}
static void nvic_sysreg_write(void *opaque, target_phys_addr_t addr,
static void nvic_sysreg_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
uint32_t offset = addr;

8
hw/axis_dev88.c
View File

@ -47,7 +47,7 @@ struct nand_state_t
};
static struct nand_state_t nand_state;
static uint64_t nand_read(void *opaque, target_phys_addr_t addr, unsigned size)
static uint64_t nand_read(void *opaque, hwaddr addr, unsigned size)
{
struct nand_state_t *s = opaque;
uint32_t r;
@ -62,7 +62,7 @@ static uint64_t nand_read(void *opaque, target_phys_addr_t addr, unsigned size)
}
static void
nand_write(void *opaque, target_phys_addr_t addr, uint64_t value,
nand_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
struct nand_state_t *s = opaque;
@ -166,7 +166,7 @@ static struct gpio_state_t
uint32_t regs[0x5c / 4];
} gpio_state;
static uint64_t gpio_read(void *opaque, target_phys_addr_t addr, unsigned size)
static uint64_t gpio_read(void *opaque, hwaddr addr, unsigned size)
{
struct gpio_state_t *s = opaque;
uint32_t r = 0;
@ -195,7 +195,7 @@ static uint64_t gpio_read(void *opaque, target_phys_addr_t addr, unsigned size)
D(printf("%s %x=%x\n", __func__, addr, r));
}
static void gpio_write(void *opaque, target_phys_addr_t addr, uint64_t value,
static void gpio_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
struct gpio_state_t *s = opaque;

38
hw/bonito.c
View File

@ -211,12 +211,12 @@ typedef struct PCIBonitoState
MemoryRegion iomem_ldma;
MemoryRegion iomem_cop;
target_phys_addr_t bonito_pciio_start;
target_phys_addr_t bonito_pciio_length;
hwaddr bonito_pciio_start;
hwaddr bonito_pciio_length;
int bonito_pciio_handle;
target_phys_addr_t bonito_localio_start;
target_phys_addr_t bonito_localio_length;
hwaddr bonito_localio_start;
hwaddr bonito_localio_length;
int bonito_localio_handle;
} PCIBonitoState;
@ -232,7 +232,7 @@ struct BonitoState {
PCIBonitoState *pci_dev;
};
static void bonito_writel(void *opaque, target_phys_addr_t addr,
static void bonito_writel(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
PCIBonitoState *s = opaque;
@ -295,7 +295,7 @@ static void bonito_writel(void *opaque, target_phys_addr_t addr,
}
}
static uint64_t bonito_readl(void *opaque, target_phys_addr_t addr,
static uint64_t bonito_readl(void *opaque, hwaddr addr,
unsigned size)
{
PCIBonitoState *s = opaque;
@ -322,7 +322,7 @@ static const MemoryRegionOps bonito_ops = {
},
};
static void bonito_pciconf_writel(void *opaque, target_phys_addr_t addr,
static void bonito_pciconf_writel(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
PCIBonitoState *s = opaque;
@ -332,7 +332,7 @@ static void bonito_pciconf_writel(void *opaque, target_phys_addr_t addr,
d->config_write(d, addr, val, 4);
}
static uint64_t bonito_pciconf_readl(void *opaque, target_phys_addr_t addr,
static uint64_t bonito_pciconf_readl(void *opaque, hwaddr addr,
unsigned size)
{
@ -355,7 +355,7 @@ static const MemoryRegionOps bonito_pciconf_ops = {
},
};
static uint64_t bonito_ldma_readl(void *opaque, target_phys_addr_t addr,
static uint64_t bonito_ldma_readl(void *opaque, hwaddr addr,
unsigned size)
{
uint32_t val;
@ -366,7 +366,7 @@ static uint64_t bonito_ldma_readl(void *opaque, target_phys_addr_t addr,
return val;
}
static void bonito_ldma_writel(void *opaque, target_phys_addr_t addr,
static void bonito_ldma_writel(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
PCIBonitoState *s = opaque;
@ -384,7 +384,7 @@ static const MemoryRegionOps bonito_ldma_ops = {
},
};
static uint64_t bonito_cop_readl(void *opaque, target_phys_addr_t addr,
static uint64_t bonito_cop_readl(void *opaque, hwaddr addr,
unsigned size)
{
uint32_t val;
@ -395,7 +395,7 @@ static uint64_t bonito_cop_readl(void *opaque, target_phys_addr_t addr,
return val;
}
static void bonito_cop_writel(void *opaque, target_phys_addr_t addr,
static void bonito_cop_writel(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
PCIBonitoState *s = opaque;
@ -413,7 +413,7 @@ static const MemoryRegionOps bonito_cop_ops = {
},
};
static uint32_t bonito_sbridge_pciaddr(void *opaque, target_phys_addr_t addr)
static uint32_t bonito_sbridge_pciaddr(void *opaque, hwaddr addr)
{
PCIBonitoState *s = opaque;
PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
@ -449,7 +449,7 @@ static uint32_t bonito_sbridge_pciaddr(void *opaque, target_phys_addr_t addr)
return pciaddr;
}
static void bonito_spciconf_writeb(void *opaque, target_phys_addr_t addr,
static void bonito_spciconf_writeb(void *opaque, hwaddr addr,
uint32_t val)
{
PCIBonitoState *s = opaque;
@ -475,7 +475,7 @@ static void bonito_spciconf_writeb(void *opaque, target_phys_addr_t addr,
pci_set_word(d->config + PCI_STATUS, status);
}
static void bonito_spciconf_writew(void *opaque, target_phys_addr_t addr,
static void bonito_spciconf_writew(void *opaque, hwaddr addr,
uint32_t val)
{
PCIBonitoState *s = opaque;
@ -503,7 +503,7 @@ static void bonito_spciconf_writew(void *opaque, target_phys_addr_t addr,
pci_set_word(d->config + PCI_STATUS, status);
}
static void bonito_spciconf_writel(void *opaque, target_phys_addr_t addr,
static void bonito_spciconf_writel(void *opaque, hwaddr addr,
uint32_t val)
{
PCIBonitoState *s = opaque;
@ -531,7 +531,7 @@ static void bonito_spciconf_writel(void *opaque, target_phys_addr_t addr,
pci_set_word(d->config + PCI_STATUS, status);
}
static uint32_t bonito_spciconf_readb(void *opaque, target_phys_addr_t addr)
static uint32_t bonito_spciconf_readb(void *opaque, hwaddr addr)
{
PCIBonitoState *s = opaque;
PCIDevice *d = PCI_DEVICE(s);
@ -557,7 +557,7 @@ static uint32_t bonito_spciconf_readb(void *opaque, target_phys_addr_t addr)
return pci_data_read(phb->bus, phb->config_reg, 1);
}
static uint32_t bonito_spciconf_readw(void *opaque, target_phys_addr_t addr)
static uint32_t bonito_spciconf_readw(void *opaque, hwaddr addr)
{
PCIBonitoState *s = opaque;
PCIDevice *d = PCI_DEVICE(s);
@ -585,7 +585,7 @@ static uint32_t bonito_spciconf_readw(void *opaque, target_phys_addr_t addr)
return pci_data_read(phb->bus, phb->config_reg, 2);
}
static uint32_t bonito_spciconf_readl(void *opaque, target_phys_addr_t addr)
static uint32_t bonito_spciconf_readl(void *opaque, hwaddr addr)
{
PCIBonitoState *s = opaque;
PCIDevice *d = PCI_DEVICE(s);

8
hw/cadence_gem.c
View File

@ -605,7 +605,7 @@ static int gem_mac_address_filter(GemState *s, const uint8_t *packet)
static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
{
unsigned desc[2];
target_phys_addr_t packet_desc_addr, last_desc_addr;
hwaddr packet_desc_addr, last_desc_addr;
GemState *s;
unsigned rxbufsize, bytes_to_copy;
unsigned rxbuf_offset;
@ -824,7 +824,7 @@ static void gem_transmit_updatestats(GemState *s, const uint8_t *packet,
static void gem_transmit(GemState *s)
{
unsigned desc[2];
target_phys_addr_t packet_desc_addr;
hwaddr packet_desc_addr;
uint8_t tx_packet[2048];
uint8_t *p;
unsigned total_bytes;
@ -1021,7 +1021,7 @@ static void gem_phy_write(GemState *s, unsigned reg_num, uint16_t val)
* gem_read32:
* Read a GEM register.
*/
static uint64_t gem_read(void *opaque, target_phys_addr_t offset, unsigned size)
static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
{
GemState *s;
uint32_t retval;
@ -1067,7 +1067,7 @@ static uint64_t gem_read(void *opaque, target_phys_addr_t offset, unsigned size)
* gem_write32:
* Write a GEM register.
*/
static void gem_write(void *opaque, target_phys_addr_t offset, uint64_t val,
static void gem_write(void *opaque, hwaddr offset, uint64_t val,
unsigned size)
{
GemState *s = (GemState *)opaque;

8
hw/cadence_ttc.c
View File

@ -76,7 +76,7 @@ static void cadence_timer_update(CadenceTimerState *s)
}
static CadenceTimerState *cadence_timer_from_addr(void *opaque,
target_phys_addr_t offset)
hwaddr offset)
{
unsigned int index;
CadenceTTCState *s = (CadenceTTCState *)opaque;
@ -224,7 +224,7 @@ static void cadence_timer_tick(void *opaque)
cadence_timer_run(s);
}
static uint32_t cadence_ttc_read_imp(void *opaque, target_phys_addr_t offset)
static uint32_t cadence_ttc_read_imp(void *opaque, hwaddr offset)
{
CadenceTimerState *s = cadence_timer_from_addr(opaque, offset);
uint32_t value;
@ -297,7 +297,7 @@ static uint32_t cadence_ttc_read_imp(void *opaque, target_phys_addr_t offset)
}
}
static uint64_t cadence_ttc_read(void *opaque, target_phys_addr_t offset,
static uint64_t cadence_ttc_read(void *opaque, hwaddr offset,
unsigned size)
{
uint32_t ret = cadence_ttc_read_imp(opaque, offset);
@ -306,7 +306,7 @@ static uint64_t cadence_ttc_read(void *opaque, target_phys_addr_t offset,
return ret;
}
static void cadence_ttc_write(void *opaque, target_phys_addr_t offset,
static void cadence_ttc_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
CadenceTimerState *s = cadence_timer_from_addr(opaque, offset);

4
hw/cadence_uart.c
View File

@ -354,7 +354,7 @@ static void uart_read_rx_fifo(UartState *s, uint32_t *c)
uart_update_status(s);
}
static void uart_write(void *opaque, target_phys_addr_t offset,
static void uart_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
UartState *s = (UartState *)opaque;
@ -397,7 +397,7 @@ static void uart_write(void *opaque, target_phys_addr_t offset,
}
}
static uint64_t uart_read(void *opaque, target_phys_addr_t offset,
static uint64_t uart_read(void *opaque, hwaddr offset,
unsigned size)
{
UartState *s = (UartState *)opaque;

16
hw/cirrus_vga.c
View File

@ -1952,7 +1952,7 @@ static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
***************************************/
static uint64_t cirrus_vga_mem_read(void *opaque,
target_phys_addr_t addr,
hwaddr addr,
uint32_t size)
{
CirrusVGAState *s = opaque;
@ -1996,7 +1996,7 @@ static uint64_t cirrus_vga_mem_read(void *opaque,
}
static void cirrus_vga_mem_write(void *opaque,
target_phys_addr_t addr,
hwaddr addr,
uint64_t mem_value,
uint32_t size)
{
@ -2255,7 +2255,7 @@ static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
*
***************************************/
static uint64_t cirrus_linear_read(void *opaque, target_phys_addr_t addr,
static uint64_t cirrus_linear_read(void *opaque, hwaddr addr,
unsigned size)
{
CirrusVGAState *s = opaque;
@ -2284,7 +2284,7 @@ static uint64_t cirrus_linear_read(void *opaque, target_phys_addr_t addr,
return ret;
}
static void cirrus_linear_write(void *opaque, target_phys_addr_t addr,
static void cirrus_linear_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
CirrusVGAState *s = opaque;
@ -2333,7 +2333,7 @@ static void cirrus_linear_write(void *opaque, target_phys_addr_t addr,
static uint64_t cirrus_linear_bitblt_read(void *opaque,
target_phys_addr_t addr,
hwaddr addr,
unsigned size)
{
CirrusVGAState *s = opaque;
@ -2346,7 +2346,7 @@ static uint64_t cirrus_linear_bitblt_read(void *opaque,
}
static void cirrus_linear_bitblt_write(void *opaque,
target_phys_addr_t addr,
hwaddr addr,
uint64_t val,
unsigned size)
{
@ -2640,7 +2640,7 @@ static void cirrus_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
*
***************************************/
static uint64_t cirrus_mmio_read(void *opaque, target_phys_addr_t addr,
static uint64_t cirrus_mmio_read(void *opaque, hwaddr addr,
unsigned size)
{
CirrusVGAState *s = opaque;
@ -2652,7 +2652,7 @@ static uint64_t cirrus_mmio_read(void *opaque, target_phys_addr_t addr,
}
}
static void cirrus_mmio_write(void *opaque, target_phys_addr_t addr,
static void cirrus_mmio_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
CirrusVGAState *s = opaque;

2
hw/cris-boot.h
View File

@ -5,7 +5,7 @@ struct cris_load_info
const char *cmdline;
int image_size;
target_phys_addr_t entry;
hwaddr entry;
};
void cris_load_image(CRISCPU *cpu, struct cris_load_info *li);

4
hw/cs4231.c
View File

@ -55,7 +55,7 @@ static void cs_reset(DeviceState *d)
s->dregs[25] = CS_VER;
}
static uint64_t cs_mem_read(void *opaque, target_phys_addr_t addr,
static uint64_t cs_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
CSState *s = opaque;
@ -82,7 +82,7 @@ static uint64_t cs_mem_read(void *opaque, target_phys_addr_t addr,
return ret;
}
static void cs_mem_write(void *opaque, target_phys_addr_t addr,
static void cs_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
CSState *s = opaque;

4
hw/cs4231a.c
View File

@ -346,7 +346,7 @@ static void cs_reset_voices (CSState *s, uint32_t val)
}
}
static uint64_t cs_read (void *opaque, target_phys_addr_t addr, unsigned size)
static uint64_t cs_read (void *opaque, hwaddr addr, unsigned size)
{
CSState *s = opaque;
uint32_t saddr, iaddr, ret;
@ -383,7 +383,7 @@ static uint64_t cs_read (void *opaque, target_phys_addr_t addr, unsigned size)
return ret;
}
static void cs_write (void *opaque, target_phys_addr_t addr,
static void cs_write (void *opaque, hwaddr addr,
uint64_t val64, unsigned size)
{
CSState *s = opaque;

12
hw/cuda.c
View File

@ -252,7 +252,7 @@ static void cuda_timer1(void *opaque)
cuda_update_irq(s);
}
static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr)
static uint32_t cuda_readb(void *opaque, hwaddr addr)
{
CUDAState *s = opaque;
uint32_t val;
@ -325,7 +325,7 @@ static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr)
return val;
}
static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
static void cuda_writeb(void *opaque, hwaddr addr, uint32_t val)
{
CUDAState *s = opaque;
@ -616,20 +616,20 @@ static void cuda_receive_packet_from_host(CUDAState *s,
}
}
static void cuda_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
static void cuda_writew (void *opaque, hwaddr addr, uint32_t value)
{
}
static void cuda_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
static void cuda_writel (void *opaque, hwaddr addr, uint32_t value)
{
}
static uint32_t cuda_readw (void *opaque, target_phys_addr_t addr)
static uint32_t cuda_readw (void *opaque, hwaddr addr)
{
return 0;
}
static uint32_t cuda_readl (void *opaque, target_phys_addr_t addr)
static uint32_t cuda_readl (void *opaque, hwaddr addr)
{
return 0;
}

4
hw/dma.c
View File

@ -411,7 +411,7 @@ void DMA_register_channel (int nchan,
int DMA_read_memory (int nchan, void *buf, int pos, int len)
{
struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
if (r->mode & 0x20) {
int i;
@ -433,7 +433,7 @@ int DMA_read_memory (int nchan, void *buf, int pos, int len)
int DMA_write_memory (int nchan, void *buf, int pos, int len)
{
struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
if (r->mode & 0x20) {
int i;

18
hw/dp8393x.c
View File

@ -168,7 +168,7 @@ typedef struct dp8393xState {
int loopback_packet;
/* Memory access */
void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write);
void (*memory_rw)(void *opaque, hwaddr addr, uint8_t *buf, int len, int is_write);
void* mem_opaque;
} dp8393xState;
@ -603,7 +603,7 @@ static void dp8393x_watchdog(void *opaque)
dp8393x_update_irq(s);
}
static uint32_t dp8393x_readw(void *opaque, target_phys_addr_t addr)
static uint32_t dp8393x_readw(void *opaque, hwaddr addr)
{
dp8393xState *s = opaque;
int reg;
@ -616,13 +616,13 @@ static uint32_t dp8393x_readw(void *opaque, target_phys_addr_t addr)
return read_register(s, reg);
}
static uint32_t dp8393x_readb(void *opaque, target_phys_addr_t addr)
static uint32_t dp8393x_readb(void *opaque, hwaddr addr)
{
uint16_t v = dp8393x_readw(opaque, addr & ~0x1);
return (v >> (8 * (addr & 0x1))) & 0xff;
}
static uint32_t dp8393x_readl(void *opaque, target_phys_addr_t addr)
static uint32_t dp8393x_readl(void *opaque, hwaddr addr)
{
uint32_t v;
v = dp8393x_readw(opaque, addr);
@ -630,7 +630,7 @@ static uint32_t dp8393x_readl(void *opaque, target_phys_addr_t addr)
return v;
}
static void dp8393x_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
static void dp8393x_writew(void *opaque, hwaddr addr, uint32_t val)
{
dp8393xState *s = opaque;
int reg;
@ -644,7 +644,7 @@ static void dp8393x_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
write_register(s, reg, (uint16_t)val);
}
static void dp8393x_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
static void dp8393x_writeb(void *opaque, hwaddr addr, uint32_t val)
{
uint16_t old_val = dp8393x_readw(opaque, addr & ~0x1);
@ -659,7 +659,7 @@ static void dp8393x_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
dp8393x_writew(opaque, addr & ~0x1, val);
}
static void dp8393x_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
static void dp8393x_writel(void *opaque, hwaddr addr, uint32_t val)
{
dp8393x_writew(opaque, addr, val & 0xffff);
dp8393x_writew(opaque, addr + 2, (val >> 16) & 0xffff);
@ -879,10 +879,10 @@ static NetClientInfo net_dp83932_info = {
.cleanup = nic_cleanup,
};
void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
void dp83932_init(NICInfo *nd, hwaddr base, int it_shift,
MemoryRegion *address_space,
qemu_irq irq, void* mem_opaque,
void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write))
void (*memory_rw)(void *opaque, hwaddr addr, uint8_t *buf, int len, int is_write))
{
dp8393xState *s;

4
hw/ds1225y.c
View File

@ -34,7 +34,7 @@ typedef struct {
uint8_t *contents;
} NvRamState;
static uint64_t nvram_read(void *opaque, target_phys_addr_t addr, unsigned size)
static uint64_t nvram_read(void *opaque, hwaddr addr, unsigned size)
{
NvRamState *s = opaque;
uint32_t val;
@ -44,7 +44,7 @@ static uint64_t nvram_read(void *opaque, target_phys_addr_t addr, unsigned size)
return val;
}
static void nvram_write(void *opaque, target_phys_addr_t addr, uint64_t val,
static void nvram_write(void *opaque, hwaddr addr, uint64_t val,
unsigned size)
{
NvRamState *s = opaque;

2
hw/dummy_m68k.c
View File

@ -26,7 +26,7 @@ static void dummy_m68k_init(QEMUMachineInitArgs *args)
MemoryRegion *ram = g_new(MemoryRegion, 1);
int kernel_size;
uint64_t elf_entry;
target_phys_addr_t entry;
hwaddr entry;
if (!cpu_model)
cpu_model = "cfv4e";

8
hw/e1000.c
View File

@ -1011,7 +1011,7 @@ static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
static void
e1000_mmio_write(void *opaque, target_phys_addr_t addr, uint64_t val,
e1000_mmio_write(void *opaque, hwaddr addr, uint64_t val,
unsigned size)
{
E1000State *s = opaque;
@ -1028,7 +1028,7 @@ e1000_mmio_write(void *opaque, target_phys_addr_t addr, uint64_t val,
}
static uint64_t
e1000_mmio_read(void *opaque, target_phys_addr_t addr, unsigned size)
e1000_mmio_read(void *opaque, hwaddr addr, unsigned size)
{
E1000State *s = opaque;
unsigned int index = (addr & 0x1ffff) >> 2;
@ -1051,7 +1051,7 @@ static const MemoryRegionOps e1000_mmio_ops = {
},
};
static uint64_t e1000_io_read(void *opaque, target_phys_addr_t addr,
static uint64_t e1000_io_read(void *opaque, hwaddr addr,
unsigned size)
{
E1000State *s = opaque;
@ -1060,7 +1060,7 @@ static uint64_t e1000_io_read(void *opaque, target_phys_addr_t addr,
return 0;
}
static void e1000_io_write(void *opaque, target_phys_addr_t addr,
static void e1000_io_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
E1000State *s = opaque;

8
hw/eccmemctl.c
View File

@ -129,7 +129,7 @@ typedef struct ECCState {
uint32_t version;
} ECCState;
static void ecc_mem_write(void *opaque, target_phys_addr_t addr, uint64_t val,
static void ecc_mem_write(void *opaque, hwaddr addr, uint64_t val,
unsigned size)
{
ECCState *s = opaque;
@ -172,7 +172,7 @@ static void ecc_mem_write(void *opaque, target_phys_addr_t addr, uint64_t val,
}
}
static uint64_t ecc_mem_read(void *opaque, target_phys_addr_t addr,
static uint64_t ecc_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
ECCState *s = opaque;
@ -229,7 +229,7 @@ static const MemoryRegionOps ecc_mem_ops = {
},
};
static void ecc_diag_mem_write(void *opaque, target_phys_addr_t addr,
static void ecc_diag_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
ECCState *s = opaque;
@ -238,7 +238,7 @@ static void ecc_diag_mem_write(void *opaque, target_phys_addr_t addr,
s->diag[addr & ECC_DIAG_MASK] = val;
}
static uint64_t ecc_diag_mem_read(void *opaque, target_phys_addr_t addr,
static uint64_t ecc_diag_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
ECCState *s = opaque;

4
hw/eepro100.c
View File

@ -1578,7 +1578,7 @@ static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
}
}
static uint64_t eepro100_read(void *opaque, target_phys_addr_t addr,
static uint64_t eepro100_read(void *opaque, hwaddr addr,
unsigned size)
{
EEPRO100State *s = opaque;
@ -1591,7 +1591,7 @@ static uint64_t eepro100_read(void *opaque, target_phys_addr_t addr,
}
}
static void eepro100_write(void *opaque, target_phys_addr_t addr,
static void eepro100_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
EEPRO100State *s = opaque;

4
hw/elf_ops.h
View File

@ -62,7 +62,7 @@ static struct elf_shdr *glue(find_section, SZ)(struct elf_shdr *shdr_table,
static int glue(symfind, SZ)(const void *s0, const void *s1)
{
target_phys_addr_t addr = *(target_phys_addr_t *)s0;
hwaddr addr = *(hwaddr *)s0;
struct elf_sym *sym = (struct elf_sym *)s1;
int result = 0;
if (addr < sym->st_value) {
@ -74,7 +74,7 @@ static int glue(symfind, SZ)(const void *s0, const void *s1)
}
static const char *glue(lookup_symbol, SZ)(struct syminfo *s,
target_phys_addr_t orig_addr)
hwaddr orig_addr)
{
struct elf_sym *syms = glue(s->disas_symtab.elf, SZ);
struct elf_sym *sym;

6
hw/empty_slot.c
View File

@ -28,14 +28,14 @@ typedef struct EmptySlot {
uint64_t size;
} EmptySlot;
static uint64_t empty_slot_read(void *opaque, target_phys_addr_t addr,
static uint64_t empty_slot_read(void *opaque, hwaddr addr,
unsigned size)
{
DPRINTF("read from " TARGET_FMT_plx "\n", addr);
return 0;
}
static void empty_slot_write(void *opaque, target_phys_addr_t addr,
static void empty_slot_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
DPRINTF("write 0x%x to " TARGET_FMT_plx "\n", (unsigned)val, addr);
@ -47,7 +47,7 @@ static const MemoryRegionOps empty_slot_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
void empty_slot_init(target_phys_addr_t addr, uint64_t slot_size)
void empty_slot_init(hwaddr addr, uint64_t slot_size)
{
if (slot_size > 0) {
/* Only empty slots larger than 0 byte need handling. */

2
hw/empty_slot.h
View File

@ -1,2 +1,2 @@
/* empty_slot.c */
void empty_slot_init(target_phys_addr_t addr, uint64_t slot_size);
void empty_slot_init(hwaddr addr, uint64_t slot_size);

8
hw/escc.c
View File

@ -463,7 +463,7 @@ static void escc_update_parameters(ChannelState *s)
qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
}
static void escc_mem_write(void *opaque, target_phys_addr_t addr,
static void escc_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
SerialState *serial = opaque;
@ -565,7 +565,7 @@ static void escc_mem_write(void *opaque, target_phys_addr_t addr,
}
}
static uint64_t escc_mem_read(void *opaque, target_phys_addr_t addr,
static uint64_t escc_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
SerialState *serial = opaque;
@ -683,7 +683,7 @@ static const VMStateDescription vmstate_escc = {
}
};
MemoryRegion *escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB,
MemoryRegion *escc_init(hwaddr base, qemu_irq irqA, qemu_irq irqB,
CharDriverState *chrA, CharDriverState *chrB,
int clock, int it_shift)
{
@ -846,7 +846,7 @@ static void sunmouse_event(void *opaque,
put_queue(s, 0);
}
void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
void slavio_serial_ms_kbd_init(hwaddr base, qemu_irq irq,
int disabled, int clock, int it_shift)
{
DeviceState *dev;

4
hw/escc.h
View File

@ -1,8 +1,8 @@
/* escc.c */
#define ESCC_SIZE 4
MemoryRegion *escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB,
MemoryRegion *escc_init(hwaddr base, qemu_irq irqA, qemu_irq irqB,
CharDriverState *chrA, CharDriverState *chrB,
int clock, int it_shift);
void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
void slavio_serial_ms_kbd_init(hwaddr base, qemu_irq irq,
int disabled, int clock, int it_shift);

4
hw/esp-pci.c
View File

@ -159,7 +159,7 @@ static uint32_t esp_pci_dma_read(PCIESPState *pci, uint32_t saddr)
return val;
}
static void esp_pci_io_write(void *opaque, target_phys_addr_t addr,
static void esp_pci_io_write(void *opaque, hwaddr addr,
uint64_t val, unsigned int size)
{
PCIESPState *pci = opaque;
@ -202,7 +202,7 @@ static void esp_pci_io_write(void *opaque, target_phys_addr_t addr,
}
}
static uint64_t esp_pci_io_read(void *opaque, target_phys_addr_t addr,
static uint64_t esp_pci_io_read(void *opaque, hwaddr addr,
unsigned int size)
{
PCIESPState *pci = opaque;

8
hw/esp.c
View File

@ -550,7 +550,7 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
s->wregs[saddr] = val;
}
static bool esp_mem_accepts(void *opaque, target_phys_addr_t addr,
static bool esp_mem_accepts(void *opaque, hwaddr addr,
unsigned size, bool is_write)
{
return (size == 1) || (is_write && size == 4);
@ -585,7 +585,7 @@ typedef struct {
ESPState esp;
} SysBusESPState;
static void sysbus_esp_mem_write(void *opaque, target_phys_addr_t addr,
static void sysbus_esp_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned int size)
{
SysBusESPState *sysbus = opaque;
@ -595,7 +595,7 @@ static void sysbus_esp_mem_write(void *opaque, target_phys_addr_t addr,
esp_reg_write(&sysbus->esp, saddr, val);
}
static uint64_t sysbus_esp_mem_read(void *opaque, target_phys_addr_t addr,
static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr,
unsigned int size)
{
SysBusESPState *sysbus = opaque;
@ -612,7 +612,7 @@ static const MemoryRegionOps sysbus_esp_mem_ops = {
.valid.accepts = esp_mem_accepts,
};
void esp_init(target_phys_addr_t espaddr, int it_shift,
void esp_init(hwaddr espaddr, int it_shift,
ESPDMAMemoryReadWriteFunc dma_memory_read,
ESPDMAMemoryReadWriteFunc dma_memory_write,
void *dma_opaque, qemu_irq irq, qemu_irq *reset,

2
hw/esp.h
View File

@ -6,7 +6,7 @@
/* esp.c */
#define ESP_MAX_DEVS 7
typedef void (*ESPDMAMemoryReadWriteFunc)(void *opaque, uint8_t *buf, int len);
void esp_init(target_phys_addr_t espaddr, int it_shift,
void esp_init(hwaddr espaddr, int it_shift,
ESPDMAMemoryReadWriteFunc dma_memory_read,
ESPDMAMemoryReadWriteFunc dma_memory_write,
void *dma_opaque, qemu_irq irq, qemu_irq *reset,

2
hw/etraxfs.h
View File

@ -29,7 +29,7 @@ qemu_irq *cris_pic_init_cpu(CPUCRISState *env);
/* Instantiate an ETRAXFS Ethernet MAC. */
static inline DeviceState *
etraxfs_eth_init(NICInfo *nd, target_phys_addr_t base, int phyaddr,
etraxfs_eth_init(NICInfo *nd, hwaddr base, int phyaddr,
void *dma_out, void *dma_in)
{
DeviceState *dev;

22
hw/etraxfs_dma.c
View File

@ -212,7 +212,7 @@ static inline int channel_en(struct fs_dma_ctrl *ctrl, int c)
&& ctrl->channels[c].client;
}
static inline int fs_channel(target_phys_addr_t addr)
static inline int fs_channel(hwaddr addr)
{
/* Every channel has a 0x2000 ctrl register map. */
return addr >> 13;
@ -221,7 +221,7 @@ static inline int fs_channel(target_phys_addr_t addr)
#ifdef USE_THIS_DEAD_CODE
static void channel_load_g(struct fs_dma_ctrl *ctrl, int c)
{
target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP);
hwaddr addr = channel_reg(ctrl, c, RW_GROUP);
/* Load and decode. FIXME: handle endianness. */
cpu_physical_memory_read (addr,
@ -253,7 +253,7 @@ static void dump_d(int ch, struct dma_descr_data *d)
static void channel_load_c(struct fs_dma_ctrl *ctrl, int c)
{
target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
hwaddr addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
/* Load and decode. FIXME: handle endianness. */
cpu_physical_memory_read (addr,
@ -270,7 +270,7 @@ static void channel_load_c(struct fs_dma_ctrl *ctrl, int c)
static void channel_load_d(struct fs_dma_ctrl *ctrl, int c)
{
target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA);
/* Load and decode. FIXME: handle endianness. */
D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
@ -284,7 +284,7 @@ static void channel_load_d(struct fs_dma_ctrl *ctrl, int c)
static void channel_store_c(struct fs_dma_ctrl *ctrl, int c)
{
target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
hwaddr addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
/* Encode and store. FIXME: handle endianness. */
D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
@ -296,7 +296,7 @@ static void channel_store_c(struct fs_dma_ctrl *ctrl, int c)
static void channel_store_d(struct fs_dma_ctrl *ctrl, int c)
{
target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA);
/* Encode and store. FIXME: handle endianness. */
D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
@ -573,14 +573,14 @@ static inline int channel_in_run(struct fs_dma_ctrl *ctrl, int c)
return 0;
}
static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr)
static uint32_t dma_rinvalid (void *opaque, hwaddr addr)
{
hw_error("Unsupported short raccess. reg=" TARGET_FMT_plx "\n", addr);
return 0;
}
static uint64_t
dma_read(void *opaque, target_phys_addr_t addr, unsigned int size)
dma_read(void *opaque, hwaddr addr, unsigned int size)
{
struct fs_dma_ctrl *ctrl = opaque;
int c;
@ -612,7 +612,7 @@ dma_read(void *opaque, target_phys_addr_t addr, unsigned int size)
}
static void
dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
dma_winvalid (void *opaque, hwaddr addr, uint32_t value)
{
hw_error("Unsupported short waccess. reg=" TARGET_FMT_plx "\n", addr);
}
@ -627,7 +627,7 @@ dma_update_state(struct fs_dma_ctrl *ctrl, int c)
}
static void
dma_write(void *opaque, target_phys_addr_t addr,
dma_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
struct fs_dma_ctrl *ctrl = opaque;
@ -762,7 +762,7 @@ static void DMA_run(void *opaque)
qemu_bh_schedule_idle(etraxfs_dmac->bh);
}
void *etraxfs_dmac_init(target_phys_addr_t base, int nr_channels)
void *etraxfs_dmac_init(hwaddr base, int nr_channels)
{
struct fs_dma_ctrl *ctrl = NULL;

2
hw/etraxfs_dma.h
View File

@ -20,7 +20,7 @@ struct etraxfs_dma_client
} client;
};
void *etraxfs_dmac_init(target_phys_addr_t base, int nr_channels);
void *etraxfs_dmac_init(hwaddr base, int nr_channels);
void etraxfs_dmac_connect(void *opaque, int channel, qemu_irq *line,
int input);
void etraxfs_dmac_connect_client(void *opaque, int c,

4
hw/etraxfs_eth.c
View File

@ -374,7 +374,7 @@ static void eth_validate_duplex(struct fs_eth *eth)
}
static uint64_t
eth_read(void *opaque, target_phys_addr_t addr, unsigned int size)
eth_read(void *opaque, hwaddr addr, unsigned int size)
{
struct fs_eth *eth = opaque;
uint32_t r = 0;
@ -418,7 +418,7 @@ static void eth_update_ma(struct fs_eth *eth, int ma)
}
static void
eth_write(void *opaque, target_phys_addr_t addr,
eth_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
struct fs_eth *eth = opaque;

4
hw/etraxfs_pic.c
View File

@ -79,7 +79,7 @@ static void pic_update(struct etrax_pic *fs)
}
static uint64_t
pic_read(void *opaque, target_phys_addr_t addr, unsigned int size)
pic_read(void *opaque, hwaddr addr, unsigned int size)
{
struct etrax_pic *fs = opaque;
uint32_t rval;
@ -89,7 +89,7 @@ pic_read(void *opaque, target_phys_addr_t addr, unsigned int size)
return rval;
}
static void pic_write(void *opaque, target_phys_addr_t addr,
static void pic_write(void *opaque, hwaddr addr,
uint64_t value, unsigned int size)
{
struct etrax_pic *fs = opaque;

4
hw/etraxfs_ser.c
View File

@ -75,7 +75,7 @@ static void ser_update_irq(struct etrax_serial *s)
}
static uint64_t
ser_read(void *opaque, target_phys_addr_t addr, unsigned int size)
ser_read(void *opaque, hwaddr addr, unsigned int size)
{
struct etrax_serial *s = opaque;
D(CPUCRISState *env = s->env);
@ -110,7 +110,7 @@ ser_read(void *opaque, target_phys_addr_t addr, unsigned int size)
}
static void
ser_write(void *opaque, target_phys_addr_t addr,
ser_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
struct etrax_serial *s = opaque;

4
hw/etraxfs_timer.c
View File

@ -75,7 +75,7 @@ struct etrax_timer {
};
static uint64_t
timer_read(void *opaque, target_phys_addr_t addr, unsigned int size)
timer_read(void *opaque, hwaddr addr, unsigned int size)
{
struct etrax_timer *t = opaque;
uint32_t r = 0;
@ -242,7 +242,7 @@ static inline void timer_watchdog_update(struct etrax_timer *t, uint32_t value)
}
static void
timer_write(void *opaque, target_phys_addr_t addr,
timer_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
struct etrax_timer *t = opaque;

2
hw/exynos4210.h
View File

@ -128,7 +128,7 @@ void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev,
/*
* exynos4210 UART
*/
DeviceState *exynos4210_uart_create(target_phys_addr_t addr,
DeviceState *exynos4210_uart_create(hwaddr addr,
int fifo_size,
int channel,
CharDriverState *chr,

4
hw/exynos4210_combiner.c
View File

@ -174,7 +174,7 @@ void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev,
}
static uint64_t
exynos4210_combiner_read(void *opaque, target_phys_addr_t offset, unsigned size)
exynos4210_combiner_read(void *opaque, hwaddr offset, unsigned size)
{
struct Exynos4210CombinerState *s =
(struct Exynos4210CombinerState *)opaque;
@ -266,7 +266,7 @@ static void exynos4210_combiner_update(void *opaque, uint8_t group_n)
}
}
static void exynos4210_combiner_write(void *opaque, target_phys_addr_t offset,
static void exynos4210_combiner_write(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
struct Exynos4210CombinerState *s =

10
hw/exynos4210_fimd.c
View File

@ -290,7 +290,7 @@ struct Exynos4210fimdWindow {
uint16_t virtpage_offsize; /* VIDWADD2 register */
MemoryRegionSection mem_section; /* RAM fragment containing framebuffer */
uint8_t *host_fb_addr; /* Host pointer to window's framebuffer */
target_phys_addr_t fb_len; /* Framebuffer length */
hwaddr fb_len; /* Framebuffer length */
};
typedef struct {
@ -1110,7 +1110,7 @@ static inline int fimd_get_buffer_id(Exynos4210fimdWindow *w)
static void fimd_update_memory_section(Exynos4210fimdState *s, unsigned win)
{
Exynos4210fimdWindow *w = &s->window[win];
target_phys_addr_t fb_start_addr, fb_mapped_len;
hwaddr fb_start_addr, fb_mapped_len;
if (!s->enabled || !(w->wincon & FIMD_WINCON_ENWIN) ||
FIMD_WINDOW_PROTECTED(s->shadowcon, win)) {
@ -1243,7 +1243,7 @@ static void exynos4210_fimd_update(void *opaque)
Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
Exynos4210fimdWindow *w;
int i, line;
target_phys_addr_t fb_line_addr, inc_size;
hwaddr fb_line_addr, inc_size;
int scrn_height;
int first_line = -1, last_line = -1, scrn_width;
bool blend = false;
@ -1348,7 +1348,7 @@ static void exynos4210_fimd_reset(DeviceState *d)
s->hueoffset = 0x01800080;
}
static void exynos4210_fimd_write(void *opaque, target_phys_addr_t offset,
static void exynos4210_fimd_write(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
@ -1649,7 +1649,7 @@ static void exynos4210_fimd_write(void *opaque, target_phys_addr_t offset,
}
}
static uint64_t exynos4210_fimd_read(void *opaque, target_phys_addr_t offset,
static uint64_t exynos4210_fimd_read(void *opaque, hwaddr offset,
unsigned size)
{
Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;

4
hw/exynos4210_i2c.c
View File

@ -129,7 +129,7 @@ static void exynos4210_i2c_data_send(void *opaque)
exynos4210_i2c_raise_interrupt(s);
}
static uint64_t exynos4210_i2c_read(void *opaque, target_phys_addr_t offset,
static uint64_t exynos4210_i2c_read(void *opaque, hwaddr offset,
unsigned size)
{
Exynos4210I2CState *s = (Exynos4210I2CState *)opaque;
@ -168,7 +168,7 @@ static uint64_t exynos4210_i2c_read(void *opaque, target_phys_addr_t offset,
return value;
}
static void exynos4210_i2c_write(void *opaque, target_phys_addr_t offset,
static void exynos4210_i2c_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
Exynos4210I2CState *s = (Exynos4210I2CState *)opaque;

4
hw/exynos4210_mct.c
View File

@ -985,7 +985,7 @@ static void exynos4210_mct_reset(DeviceState *d)
}
/* Multi Core Timer read */
static uint64_t exynos4210_mct_read(void *opaque, target_phys_addr_t offset,
static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset,
unsigned size)
{
Exynos4210MCTState *s = (Exynos4210MCTState *)opaque;
@ -1098,7 +1098,7 @@ static uint64_t exynos4210_mct_read(void *opaque, target_phys_addr_t offset,
}
/* MCT write */
static void exynos4210_mct_write(void *opaque, target_phys_addr_t offset,
static void exynos4210_mct_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
Exynos4210MCTState *s = (Exynos4210MCTState *)opaque;

4
hw/exynos4210_pmu.c
View File

@ -392,7 +392,7 @@ typedef struct Exynos4210PmuState {
uint32_t reg[PMU_NUM_OF_REGISTERS];
} Exynos4210PmuState;
static uint64_t exynos4210_pmu_read(void *opaque, target_phys_addr_t offset,
static uint64_t exynos4210_pmu_read(void *opaque, hwaddr offset,
unsigned size)
{
Exynos4210PmuState *s = (Exynos4210PmuState *)opaque;
@ -411,7 +411,7 @@ static uint64_t exynos4210_pmu_read(void *opaque, target_phys_addr_t offset,
return 0;
}
static void exynos4210_pmu_write(void *opaque, target_phys_addr_t offset,
static void exynos4210_pmu_write(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
Exynos4210PmuState *s = (Exynos4210PmuState *)opaque;

4
hw/exynos4210_pwm.c
View File

@ -208,7 +208,7 @@ static void exynos4210_pwm_tick(void *opaque)
/*
* PWM Read
*/
static uint64_t exynos4210_pwm_read(void *opaque, target_phys_addr_t offset,
static uint64_t exynos4210_pwm_read(void *opaque, hwaddr offset,
unsigned size)
{
Exynos4210PWMState *s = (Exynos4210PWMState *)opaque;
@ -259,7 +259,7 @@ static uint64_t exynos4210_pwm_read(void *opaque, target_phys_addr_t offset,
/*
* PWM Write
*/
static void exynos4210_pwm_write(void *opaque, target_phys_addr_t offset,
static void exynos4210_pwm_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
Exynos4210PWMState *s = (Exynos4210PWMState *)opaque;

4
hw/exynos4210_rtc.c
View File

@ -299,7 +299,7 @@ static void exynos4210_rtc_1Hz_tick(void *opaque)
/*
* RTC Read
*/
static uint64_t exynos4210_rtc_read(void *opaque, target_phys_addr_t offset,
static uint64_t exynos4210_rtc_read(void *opaque, hwaddr offset,
unsigned size)
{
uint32_t value = 0;
@ -376,7 +376,7 @@ static uint64_t exynos4210_rtc_read(void *opaque, target_phys_addr_t offset,
/*
* RTC Write
*/
static void exynos4210_rtc_write(void *opaque, target_phys_addr_t offset,
static void exynos4210_rtc_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
Exynos4210RTCState *s = (Exynos4210RTCState *)opaque;

12
hw/exynos4210_uart.c
View File

@ -96,7 +96,7 @@
typedef struct Exynos4210UartReg {
const char *name; /* the only reason is the debug output */
target_phys_addr_t offset;
hwaddr offset;
uint32_t reset_value;
} Exynos4210UartReg;
@ -184,7 +184,7 @@ typedef struct {
#if DEBUG_UART
/* Used only for debugging inside PRINT_DEBUG_... macros */
static const char *exynos4210_uart_regname(target_phys_addr_t offset)
static const char *exynos4210_uart_regname(hwaddr offset)
{
int regs_number = sizeof(exynos4210_uart_regs) / sizeof(Exynos4210UartReg);
@ -348,7 +348,7 @@ static void exynos4210_uart_update_parameters(Exynos4210UartState *s)
s->channel, speed, parity, data_bits, stop_bits);
}
static void exynos4210_uart_write(void *opaque, target_phys_addr_t offset,
static void exynos4210_uart_write(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
Exynos4210UartState *s = (Exynos4210UartState *)opaque;
@ -423,7 +423,7 @@ static void exynos4210_uart_write(void *opaque, target_phys_addr_t offset,
break;
}
}
static uint64_t exynos4210_uart_read(void *opaque, target_phys_addr_t offset,
static uint64_t exynos4210_uart_read(void *opaque, hwaddr offset,
unsigned size)
{
Exynos4210UartState *s = (Exynos4210UartState *)opaque;
@ -581,7 +581,7 @@ static const VMStateDescription vmstate_exynos4210_uart = {
}
};
DeviceState *exynos4210_uart_create(target_phys_addr_t addr,
DeviceState *exynos4210_uart_create(hwaddr addr,
int fifo_size,
int channel,
CharDriverState *chr,
@ -617,7 +617,7 @@ DeviceState *exynos4210_uart_create(target_phys_addr_t addr,
bus = sysbus_from_qdev(dev);
qdev_init_nofail(dev);
if (addr != (target_phys_addr_t)-1) {
if (addr != (hwaddr)-1) {
sysbus_mmio_map(bus, 0, addr);
}
sysbus_connect_irq(bus, 0, irq);

8
hw/fdc.c
View File

@ -626,13 +626,13 @@ static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
}
}
static uint64_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg,
static uint64_t fdctrl_read_mem (void *opaque, hwaddr reg,
unsigned ize)
{
return fdctrl_read(opaque, (uint32_t)reg);
}
static void fdctrl_write_mem (void *opaque, target_phys_addr_t reg,
static void fdctrl_write_mem (void *opaque, hwaddr reg,
uint64_t value, unsigned size)
{
fdctrl_write(opaque, (uint32_t)reg, value);
@ -2032,7 +2032,7 @@ ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds)
}
void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
target_phys_addr_t mmio_base, DriveInfo **fds)
hwaddr mmio_base, DriveInfo **fds)
{
FDCtrl *fdctrl;
DeviceState *dev;
@ -2053,7 +2053,7 @@ void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
sysbus_mmio_map(&sys->busdev, 0, mmio_base);
}
void sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base,
DriveInfo **fds, qemu_irq *fdc_tc)
{
DeviceState *dev;

4
hw/fdc.h
View File

@ -15,8 +15,8 @@ typedef enum FDriveType {
ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds);
void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
target_phys_addr_t mmio_base, DriveInfo **fds);
void sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
hwaddr mmio_base, DriveInfo **fds);
void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base,
DriveInfo **fds, qemu_irq *fdc_tc);
FDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i);

8
hw/flash.h
View File

@ -5,18 +5,18 @@
typedef struct pflash_t pflash_t;
/* pflash_cfi01.c */
pflash_t *pflash_cfi01_register(target_phys_addr_t base,
pflash_t *pflash_cfi01_register(hwaddr base,
DeviceState *qdev, const char *name,
target_phys_addr_t size,
hwaddr size,
BlockDriverState *bs,
uint32_t sector_len, int nb_blocs, int width,
uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3, int be);
/* pflash_cfi02.c */
pflash_t *pflash_cfi02_register(target_phys_addr_t base,
pflash_t *pflash_cfi02_register(hwaddr base,
DeviceState *qdev, const char *name,
target_phys_addr_t size,
hwaddr size,
BlockDriverState *bs, uint32_t sector_len,
int nb_blocs, int nb_mappings, int width,
uint16_t id0, uint16_t id1,

4
hw/framebuffer.c
View File

@ -26,7 +26,7 @@
void framebuffer_update_display(
DisplayState *ds,
MemoryRegion *address_space,
target_phys_addr_t base,
hwaddr base,
int cols, /* Width in pixels. */
int rows, /* Height in pixels. */
int src_width, /* Length of source line, in bytes. */
@ -38,7 +38,7 @@ void framebuffer_update_display(
int *first_row, /* Input and output. */
int *last_row /* Output only */)
{
target_phys_addr_t src_len;
hwaddr src_len;
uint8_t *dest;
uint8_t *src;
uint8_t *src_base;

2
hw/framebuffer.h
View File

@ -10,7 +10,7 @@ typedef void (*drawfn)(void *, uint8_t *, const uint8_t *, int, int);
void framebuffer_update_display(
DisplayState *ds,
MemoryRegion *address_space,
target_phys_addr_t base,
hwaddr base,
int cols,
int rows,
int src_width,

16
hw/fw_cfg.c
View File

@ -258,37 +258,37 @@ static uint8_t fw_cfg_read(FWCfgState *s)
return ret;
}
static uint64_t fw_cfg_data_mem_read(void *opaque, target_phys_addr_t addr,
static uint64_t fw_cfg_data_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
return fw_cfg_read(opaque);
}
static void fw_cfg_data_mem_write(void *opaque, target_phys_addr_t addr,
static void fw_cfg_data_mem_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
fw_cfg_write(opaque, (uint8_t)value);
}
static void fw_cfg_ctl_mem_write(void *opaque, target_phys_addr_t addr,
static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
fw_cfg_select(opaque, (uint16_t)value);
}
static bool fw_cfg_ctl_mem_valid(void *opaque, target_phys_addr_t addr,
static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr,
unsigned size, bool is_write)
{
return is_write && size == 2;
}
static uint64_t fw_cfg_comb_read(void *opaque, target_phys_addr_t addr,
static uint64_t fw_cfg_comb_read(void *opaque, hwaddr addr,
unsigned size)
{
return fw_cfg_read(opaque);
}
static void fw_cfg_comb_write(void *opaque, target_phys_addr_t addr,
static void fw_cfg_comb_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
switch (size) {
@ -301,7 +301,7 @@ static void fw_cfg_comb_write(void *opaque, target_phys_addr_t addr,
}
}
static bool fw_cfg_comb_valid(void *opaque, target_phys_addr_t addr,
static bool fw_cfg_comb_valid(void *opaque, hwaddr addr,
unsigned size, bool is_write)
{
return (size == 1) || (is_write && size == 2);
@ -494,7 +494,7 @@ static void fw_cfg_machine_ready(struct Notifier *n, void *data)
}
FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
target_phys_addr_t ctl_addr, target_phys_addr_t data_addr)
hwaddr ctl_addr, hwaddr data_addr)
{
DeviceState *dev;
SysBusDevice *d;

2
hw/fw_cfg.h
View File

@ -63,7 +63,7 @@ int fw_cfg_add_callback(FWCfgState *s, uint16_t key, FWCfgCallback callback,
int fw_cfg_add_file(FWCfgState *s, const char *filename, uint8_t *data,
uint32_t len);
FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
target_phys_addr_t crl_addr, target_phys_addr_t data_addr);
hwaddr crl_addr, hwaddr data_addr);
#endif /* NO_QEMU_PROTOS */

4
hw/g364fb.c
View File

@ -362,7 +362,7 @@ write_err:
/* called for accesses to io ports */
static uint64_t g364fb_ctrl_read(void *opaque,
target_phys_addr_t addr,
hwaddr addr,
unsigned int size)
{
G364State *s = opaque;
@ -424,7 +424,7 @@ static void g364_invalidate_cursor_position(G364State *s)
}
static void g364fb_ctrl_write(void *opaque,
target_phys_addr_t addr,
hwaddr addr,
uint64_t val,
unsigned int size)
{

6
hw/grlib.h
View File

@ -41,7 +41,7 @@ void grlib_irqmp_set_irq(void *opaque, int irq, int level);
void grlib_irqmp_ack(DeviceState *dev, int intno);
static inline
DeviceState *grlib_irqmp_create(target_phys_addr_t base,
DeviceState *grlib_irqmp_create(hwaddr base,
CPUSPARCState *env,
qemu_irq **cpu_irqs,
uint32_t nr_irqs,
@ -73,7 +73,7 @@ DeviceState *grlib_irqmp_create(target_phys_addr_t base,
/* GPTimer */
static inline
DeviceState *grlib_gptimer_create(target_phys_addr_t base,
DeviceState *grlib_gptimer_create(hwaddr base,
uint32_t nr_timers,
uint32_t freq,
qemu_irq *cpu_irqs,
@ -103,7 +103,7 @@ DeviceState *grlib_gptimer_create(target_phys_addr_t base,
/* APB UART */
static inline
DeviceState *grlib_apbuart_create(target_phys_addr_t base,
DeviceState *grlib_apbuart_create(hwaddr base,
CharDriverState *serial,
qemu_irq irq)
{

4
hw/grlib_apbuart.c
View File

@ -151,7 +151,7 @@ static void grlib_apbuart_event(void *opaque, int event)
}
static uint64_t grlib_apbuart_read(void *opaque, target_phys_addr_t addr,
static uint64_t grlib_apbuart_read(void *opaque, hwaddr addr,
unsigned size)
{
UART *uart = opaque;
@ -181,7 +181,7 @@ static uint64_t grlib_apbuart_read(void *opaque, target_phys_addr_t addr,
}
}
static void grlib_apbuart_write(void *opaque, target_phys_addr_t addr,
static void grlib_apbuart_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
UART *uart = opaque;

8
hw/grlib_gptimer.c
View File

@ -155,11 +155,11 @@ static void grlib_gptimer_hit(void *opaque)
}
}
static uint64_t grlib_gptimer_read(void *opaque, target_phys_addr_t addr,
static uint64_t grlib_gptimer_read(void *opaque, hwaddr addr,
unsigned size)
{
GPTimerUnit *unit = opaque;
target_phys_addr_t timer_addr;
hwaddr timer_addr;
int id;
uint32_t value = 0;
@ -214,11 +214,11 @@ static uint64_t grlib_gptimer_read(void *opaque, target_phys_addr_t addr,
return 0;
}
static void grlib_gptimer_write(void *opaque, target_phys_addr_t addr,
static void grlib_gptimer_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
GPTimerUnit *unit = opaque;
target_phys_addr_t timer_addr;
hwaddr timer_addr;
int id;
addr &= 0xff;

4
hw/grlib_irqmp.c
View File

@ -162,7 +162,7 @@ void grlib_irqmp_set_irq(void *opaque, int irq, int level)
}
}
static uint64_t grlib_irqmp_read(void *opaque, target_phys_addr_t addr,
static uint64_t grlib_irqmp_read(void *opaque, hwaddr addr,
unsigned size)
{
IRQMP *irqmp = opaque;
@ -226,7 +226,7 @@ static uint64_t grlib_irqmp_read(void *opaque, target_phys_addr_t addr,
return 0;
}
static void grlib_irqmp_write(void *opaque, target_phys_addr_t addr,
static void grlib_irqmp_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
IRQMP *irqmp = opaque;

20
hw/gt64xxx.c
View File

@ -225,8 +225,8 @@
#define GT_PCI1_SERR1MASK (0xca8 >> 2)
#define PCI_MAPPING_ENTRY(regname) \
target_phys_addr_t regname ##_start; \
target_phys_addr_t regname ##_length; \
hwaddr regname ##_start; \
hwaddr regname ##_length; \
MemoryRegion regname ##_mem
#define TYPE_GT64120_PCI_HOST_BRIDGE "gt64120"
@ -245,11 +245,11 @@ typedef struct GT64120State {
/* Adjust range to avoid touching space which isn't mappable via PCI */
/* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
0x1fc00000 - 0x1fd00000 */
static void check_reserved_space (target_phys_addr_t *start,
target_phys_addr_t *length)
static void check_reserved_space (hwaddr *start,
hwaddr *length)
{
target_phys_addr_t begin = *start;
target_phys_addr_t end = *start + *length;
hwaddr begin = *start;
hwaddr end = *start + *length;
if (end >= 0x1e000000LL && end < 0x1f100000LL)
end = 0x1e000000LL;
@ -271,8 +271,8 @@ static void check_reserved_space (target_phys_addr_t *start,
static void gt64120_isd_mapping(GT64120State *s)
{
target_phys_addr_t start = s->regs[GT_ISD] << 21;
target_phys_addr_t length = 0x1000;
hwaddr start = s->regs[GT_ISD] << 21;
hwaddr length = 0x1000;
if (s->ISD_length) {
memory_region_del_subregion(get_system_memory(), &s->ISD_mem);
@ -311,7 +311,7 @@ static void gt64120_pci_mapping(GT64120State *s)
}
}
static void gt64120_writel (void *opaque, target_phys_addr_t addr,
static void gt64120_writel (void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
GT64120State *s = opaque;
@ -594,7 +594,7 @@ static void gt64120_writel (void *opaque, target_phys_addr_t addr,
}
static uint64_t gt64120_readl (void *opaque,
target_phys_addr_t addr, unsigned size)
hwaddr addr, unsigned size)
{
GT64120State *s = opaque;
PCIHostState *phb = PCI_HOST_BRIDGE(s);

4
hw/heathrow_pic.c
View File

@ -63,7 +63,7 @@ static void heathrow_pic_update(HeathrowPICS *s)
}
}
static void pic_write(void *opaque, target_phys_addr_t addr,
static void pic_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
HeathrowPICS *s = opaque;
@ -91,7 +91,7 @@ static void pic_write(void *opaque, target_phys_addr_t addr,
}
}
static uint64_t pic_read(void *opaque, target_phys_addr_t addr,
static uint64_t pic_read(void *opaque, hwaddr addr,
unsigned size)
{
HeathrowPICS *s = opaque;

4
hw/highbank.c
View File

@ -79,7 +79,7 @@ static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
}
#define NUM_REGS 0x200
static void hb_regs_write(void *opaque, target_phys_addr_t offset,
static void hb_regs_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
uint32_t *regs = opaque;
@ -95,7 +95,7 @@ static void hb_regs_write(void *opaque, target_phys_addr_t offset,
regs[offset/4] = value;
}
static uint64_t hb_regs_read(void *opaque, target_phys_addr_t offset,
static uint64_t hb_regs_read(void *opaque, hwaddr offset,
unsigned size)
{
uint32_t *regs = opaque;

8
hw/hpet.c
View File

@ -370,20 +370,20 @@ static void hpet_del_timer(HPETTimer *t)
}
#ifdef HPET_DEBUG
static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr)
static uint32_t hpet_ram_readb(void *opaque, hwaddr addr)
{
printf("qemu: hpet_read b at %" PRIx64 "\n", addr);
return 0;
}
static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr)
static uint32_t hpet_ram_readw(void *opaque, hwaddr addr)
{
printf("qemu: hpet_read w at %" PRIx64 "\n", addr);
return 0;
}
#endif
static uint64_t hpet_ram_read(void *opaque, target_phys_addr_t addr,
static uint64_t hpet_ram_read(void *opaque, hwaddr addr,
unsigned size)
{
HPETState *s = opaque;
@ -455,7 +455,7 @@ static uint64_t hpet_ram_read(void *opaque, target_phys_addr_t addr,
return 0;
}
static void hpet_ram_write(void *opaque, target_phys_addr_t addr,
static void hpet_ram_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
int i;

8
hw/i82378.c
View File

@ -59,7 +59,7 @@ static const VMStateDescription vmstate_pci_i82378 = {
},
};
static void i82378_io_write(void *opaque, target_phys_addr_t addr,
static void i82378_io_write(void *opaque, hwaddr addr,
uint64_t value, unsigned int size)
{
switch (size) {
@ -83,7 +83,7 @@ static void i82378_io_write(void *opaque, target_phys_addr_t addr,
}
}
static uint64_t i82378_io_read(void *opaque, target_phys_addr_t addr,
static uint64_t i82378_io_read(void *opaque, hwaddr addr,
unsigned int size)
{
DPRINTF("%s: " TARGET_FMT_plx "\n", __func__, addr);
@ -105,7 +105,7 @@ static const MemoryRegionOps i82378_io_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
static void i82378_mem_write(void *opaque, target_phys_addr_t addr,
static void i82378_mem_write(void *opaque, hwaddr addr,
uint64_t value, unsigned int size)
{
switch (size) {
@ -129,7 +129,7 @@ static void i82378_mem_write(void *opaque, target_phys_addr_t addr,
}
}
static uint64_t i82378_mem_read(void *opaque, target_phys_addr_t addr,
static uint64_t i82378_mem_read(void *opaque, hwaddr addr,
unsigned int size)
{
DPRINTF("%s: " TARGET_FMT_plx "\n", __func__, addr);

8
hw/i8259.c
View File

@ -235,7 +235,7 @@ static void pic_reset(DeviceState *dev)
pic_init_reset(s);
}
static void pic_ioport_write(void *opaque, target_phys_addr_t addr64,
static void pic_ioport_write(void *opaque, hwaddr addr64,
uint64_t val64, unsigned size)
{
PICCommonState *s = opaque;
@ -329,7 +329,7 @@ static void pic_ioport_write(void *opaque, target_phys_addr_t addr64,
}
}
static uint64_t pic_ioport_read(void *opaque, target_phys_addr_t addr,
static uint64_t pic_ioport_read(void *opaque, hwaddr addr,
unsigned size)
{
PICCommonState *s = opaque;
@ -366,14 +366,14 @@ int pic_get_output(DeviceState *d)
return (pic_get_irq(s) >= 0);
}
static void elcr_ioport_write(void *opaque, target_phys_addr_t addr,
static void elcr_ioport_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
PICCommonState *s = opaque;
s->elcr = val & s->elcr_mask;
}
static uint64_t elcr_ioport_read(void *opaque, target_phys_addr_t addr,
static uint64_t elcr_ioport_read(void *opaque, hwaddr addr,
unsigned size)
{
PICCommonState *s = opaque;

2
hw/ide.h
View File

@ -24,7 +24,7 @@ MemoryRegion *pmac_ide_init (DriveInfo **hd_table, qemu_irq irq,
void *dbdma, int channel, qemu_irq dma_irq);
/* ide-mmio.c */
void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
void mmio_ide_init (hwaddr membase, hwaddr membase2,
MemoryRegion *address_space,
qemu_irq irq, int shift,
DriveInfo *hd0, DriveInfo *hd1);

10
hw/ide/ahci.c
View File

@ -174,7 +174,7 @@ static void ahci_trigger_irq(AHCIState *s, AHCIDevice *d,
static void map_page(uint8_t **ptr, uint64_t addr, uint32_t wanted)
{
target_phys_addr_t len = wanted;
hwaddr len = wanted;
if (*ptr) {
cpu_physical_memory_unmap(*ptr, len, 1, len);
@ -279,7 +279,7 @@ static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val)
}
}
static uint64_t ahci_mem_read(void *opaque, target_phys_addr_t addr,
static uint64_t ahci_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
AHCIState *s = opaque;
@ -317,7 +317,7 @@ static uint64_t ahci_mem_read(void *opaque, target_phys_addr_t addr,
static void ahci_mem_write(void *opaque, target_phys_addr_t addr,
static void ahci_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
AHCIState *s = opaque;
@ -373,7 +373,7 @@ static const MemoryRegionOps ahci_mem_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
static uint64_t ahci_idp_read(void *opaque, target_phys_addr_t addr,
static uint64_t ahci_idp_read(void *opaque, hwaddr addr,
unsigned size)
{
AHCIState *s = opaque;
@ -389,7 +389,7 @@ static uint64_t ahci_idp_read(void *opaque, target_phys_addr_t addr,
}
}
static void ahci_idp_write(void *opaque, target_phys_addr_t addr,
static void ahci_idp_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
AHCIState *s = opaque;

12
hw/ide/cmd646.c
View File

@ -43,7 +43,7 @@
static void cmd646_update_irq(PCIIDEState *d);
static uint64_t cmd646_cmd_read(void *opaque, target_phys_addr_t addr,
static uint64_t cmd646_cmd_read(void *opaque, hwaddr addr,
unsigned size)
{
CMD646BAR *cmd646bar = opaque;
@ -54,7 +54,7 @@ static uint64_t cmd646_cmd_read(void *opaque, target_phys_addr_t addr,
return ide_status_read(cmd646bar->bus, addr + 2);
}
static void cmd646_cmd_write(void *opaque, target_phys_addr_t addr,
static void cmd646_cmd_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
CMD646BAR *cmd646bar = opaque;
@ -71,7 +71,7 @@ static const MemoryRegionOps cmd646_cmd_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
static uint64_t cmd646_data_read(void *opaque, target_phys_addr_t addr,
static uint64_t cmd646_data_read(void *opaque, hwaddr addr,
unsigned size)
{
CMD646BAR *cmd646bar = opaque;
@ -88,7 +88,7 @@ static uint64_t cmd646_data_read(void *opaque, target_phys_addr_t addr,
return ((uint64_t)1 << (size * 8)) - 1;
}
static void cmd646_data_write(void *opaque, target_phys_addr_t addr,
static void cmd646_data_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
CMD646BAR *cmd646bar = opaque;
@ -121,7 +121,7 @@ static void setup_cmd646_bar(PCIIDEState *d, int bus_num)
memory_region_init_io(&bar->data, &cmd646_data_ops, bar, "cmd646-data", 8);
}
static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr,
static uint64_t bmdma_read(void *opaque, hwaddr addr,
unsigned size)
{
BMDMAState *bm = opaque;
@ -159,7 +159,7 @@ static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr,
return val;
}
static void bmdma_write(void *opaque, target_phys_addr_t addr,
static void bmdma_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
BMDMAState *bm = opaque;

12
hw/ide/macio.c
View File

@ -198,7 +198,7 @@ static void pmac_ide_flush(DBDMA_io *io)
/* PowerMac IDE memory IO */
static void pmac_ide_writeb (void *opaque,
target_phys_addr_t addr, uint32_t val)
hwaddr addr, uint32_t val)
{
MACIOIDEState *d = opaque;
@ -216,7 +216,7 @@ static void pmac_ide_writeb (void *opaque,
}
}
static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr)
static uint32_t pmac_ide_readb (void *opaque,hwaddr addr)
{
uint8_t retval;
MACIOIDEState *d = opaque;
@ -238,7 +238,7 @@ static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr)
}
static void pmac_ide_writew (void *opaque,
target_phys_addr_t addr, uint32_t val)
hwaddr addr, uint32_t val)
{
MACIOIDEState *d = opaque;
@ -249,7 +249,7 @@ static void pmac_ide_writew (void *opaque,
}
}
static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr)
static uint32_t pmac_ide_readw (void *opaque,hwaddr addr)
{
uint16_t retval;
MACIOIDEState *d = opaque;
@ -265,7 +265,7 @@ static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr)
}
static void pmac_ide_writel (void *opaque,
target_phys_addr_t addr, uint32_t val)
hwaddr addr, uint32_t val)
{
MACIOIDEState *d = opaque;
@ -276,7 +276,7 @@ static void pmac_ide_writel (void *opaque,
}
}
static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr)
static uint32_t pmac_ide_readl (void *opaque,hwaddr addr)
{
uint32_t retval;
MACIOIDEState *d = opaque;

10
hw/ide/mmio.c
View File

@ -47,7 +47,7 @@ static void mmio_ide_reset(void *opaque)
ide_bus_reset(&s->bus);
}
static uint64_t mmio_ide_read(void *opaque, target_phys_addr_t addr,
static uint64_t mmio_ide_read(void *opaque, hwaddr addr,
unsigned size)
{
MMIOState *s = opaque;
@ -58,7 +58,7 @@ static uint64_t mmio_ide_read(void *opaque, target_phys_addr_t addr,
return ide_data_readw(&s->bus, 0);
}
static void mmio_ide_write(void *opaque, target_phys_addr_t addr,
static void mmio_ide_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MMIOState *s = opaque;
@ -75,14 +75,14 @@ static const MemoryRegionOps mmio_ide_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static uint64_t mmio_ide_status_read(void *opaque, target_phys_addr_t addr,
static uint64_t mmio_ide_status_read(void *opaque, hwaddr addr,
unsigned size)
{
MMIOState *s= opaque;
return ide_status_read(&s->bus, 0);
}
static void mmio_ide_cmd_write(void *opaque, target_phys_addr_t addr,
static void mmio_ide_cmd_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MMIOState *s = opaque;
@ -107,7 +107,7 @@ static const VMStateDescription vmstate_ide_mmio = {
}
};
void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
void mmio_ide_init (hwaddr membase, hwaddr membase2,
MemoryRegion *address_space,
qemu_irq irq, int shift,
DriveInfo *hd0, DriveInfo *hd1)

4
hw/ide/pci.c
View File

@ -327,7 +327,7 @@ void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val)
bm->cmd = val & 0x09;
}
static uint64_t bmdma_addr_read(void *opaque, target_phys_addr_t addr,
static uint64_t bmdma_addr_read(void *opaque, hwaddr addr,
unsigned width)
{
BMDMAState *bm = opaque;
@ -341,7 +341,7 @@ static uint64_t bmdma_addr_read(void *opaque, target_phys_addr_t addr,
return data;
}
static void bmdma_addr_write(void *opaque, target_phys_addr_t addr,
static void bmdma_addr_write(void *opaque, hwaddr addr,
uint64_t data, unsigned width)
{
BMDMAState *bm = opaque;

4
hw/ide/piix.c
View File

@ -33,7 +33,7 @@
#include <hw/ide/pci.h>
static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr, unsigned size)
static uint64_t bmdma_read(void *opaque, hwaddr addr, unsigned size)
{
BMDMAState *bm = opaque;
uint32_t val;
@ -59,7 +59,7 @@ static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr, unsigned size)
return val;
}
static void bmdma_write(void *opaque, target_phys_addr_t addr,
static void bmdma_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
BMDMAState *bm = opaque;

4
hw/ide/via.c
View File

@ -33,7 +33,7 @@
#include <hw/ide/pci.h>
static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr,
static uint64_t bmdma_read(void *opaque, hwaddr addr,
unsigned size)
{
BMDMAState *bm = opaque;
@ -60,7 +60,7 @@ static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr,
return val;
}
static void bmdma_write(void *opaque, target_phys_addr_t addr,
static void bmdma_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
BMDMAState *bm = opaque;

6
hw/imx.h
View File

@ -11,7 +11,7 @@
#ifndef IMX_H
#define IMX_H
void imx_serial_create(int uart, const target_phys_addr_t addr, qemu_irq irq);
void imx_serial_create(int uart, const hwaddr addr, qemu_irq irq);
typedef enum {
NOCLK,
@ -23,10 +23,10 @@ typedef enum {
uint32_t imx_clock_frequency(DeviceState *s, IMXClk clock);
void imx_timerp_create(const target_phys_addr_t addr,
void imx_timerp_create(const hwaddr addr,
qemu_irq irq,
DeviceState *ccm);
void imx_timerg_create(const target_phys_addr_t addr,
void imx_timerg_create(const hwaddr addr,
qemu_irq irq,
DeviceState *ccm);

4
hw/imx_avic.c
View File

@ -152,7 +152,7 @@ static void imx_avic_set_irq(void *opaque, int irq, int level)
static uint64_t imx_avic_read(void *opaque,
target_phys_addr_t offset, unsigned size)
hwaddr offset, unsigned size)
{
IMXAVICState *s = (IMXAVICState *)opaque;
@ -259,7 +259,7 @@ static uint64_t imx_avic_read(void *opaque,
}
}
static void imx_avic_write(void *opaque, target_phys_addr_t offset,
static void imx_avic_write(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
IMXAVICState *s = (IMXAVICState *)opaque;

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