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pc,virtio: fixes 

Several bugfixes, they all look very safe to me. Revert
 seed support since we aren't any closer to a proper fix.
 
 Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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Merge tag 'for_upstream' of git://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging

pc,virtio: fixes

Several bugfixes, they all look very safe to me. Revert
seed support since we aren't any closer to a proper fix.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

# -----BEGIN PGP SIGNATURE-----
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# YXQuY29tAAoJECgfDbjSjVRpKCkH/2KjgmgG2BpeSm5WHm2ySMZ8aNactDhjc/zg
# S2iFMPRx6at4fagErT0h4hdI2SunbWz+dH8v6wdPmiIX//HNRUiZPW6vItib3aaN
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# gpg: Signature made Wed 17 Aug 2022 10:08:20 AM PDT
# gpg:                using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
# gpg:                issuer "mst@redhat.com"
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [undefined]
# gpg:                 aka "Michael S. Tsirkin <mst@redhat.com>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17  0970 C350 3912 AFBE 8E67
#      Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA  8A0D 281F 0DB8 D28D 5469

* tag 'for_upstream' of git://git.kernel.org/pub/scm/virt/kvm/mst/qemu:
  virtio-pci: don't touch pci on virtio reset
  tests: acpi: silence applesmc warning about invalid key
  hw/cxl: Correctly handle variable sized mailbox input payloads.
  hw/cxl: Fix Get LSA input payload size which should be 8 bytes.
  hw/cxl: Add stub write function for RO MemoryRegionOps entries.
  hw/cxl: Fix wrong query of target ports
  hw/cxl: Fix memory leak in error paths
  x86: disable rng seeding via setup_data
  hw/virtio: fix vhost_user_read tracepoint
  hw/virtio: handle un-configured shutdown in virtio-pci
  hw/virtio: gracefully handle unset vhost_dev vdev
  virtio-scsi: fix race in virtio_scsi_dataplane_start()

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-08-18 00:18:50 -07:00
parent c7208a6e0d 9afb4177d6
commit a89a946f01
12 changed files with 62 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
hw/block/dataplane/virtio-blk.c
View File

@ -219,6 +219,11 @@ int virtio_blk_data_plane_start(VirtIODevice *vdev)
memory_region_transaction_commit();
/*
* These fields are visible to the IOThread so we rely on implicit barriers
* in aio_context_acquire() on the write side and aio_notify_accept() on
* the read side.
*/
s->starting = false;
vblk->dataplane_started = true;
trace_virtio_blk_data_plane_start(s);

12
hw/cxl/cxl-device-utils.c
View File

@ -141,9 +141,15 @@ static uint64_t mdev_reg_read(void *opaque, hwaddr offset, unsigned size)
return retval;
}
static void ro_reg_write(void *opaque, hwaddr offset, uint64_t value,
unsigned size)
{
/* Many register sets are read only */
}
static const MemoryRegionOps mdev_ops = {
.read = mdev_reg_read,
.write = NULL, /* memory device register is read only */
.write = ro_reg_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 1,
@ -173,7 +179,7 @@ static const MemoryRegionOps mailbox_ops = {
static const MemoryRegionOps dev_ops = {
.read = dev_reg_read,
.write = NULL, /* status register is read only */
.write = ro_reg_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 1,
@ -188,7 +194,7 @@ static const MemoryRegionOps dev_ops = {
static const MemoryRegionOps caps_ops = {
.read = caps_reg_read,
.write = NULL, /* caps registers are read only */
.write = ro_reg_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 1,

17
hw/cxl/cxl-host.c
View File

@ -26,7 +26,7 @@ static void cxl_fixed_memory_window_config(CXLState *cxl_state,
CXLFixedMemoryWindowOptions *object,
Error **errp)
{
CXLFixedWindow *fw = g_malloc0(sizeof(*fw));
g_autofree CXLFixedWindow *fw = g_malloc0(sizeof(*fw));
strList *target;
int i;
@ -64,7 +64,8 @@ static void cxl_fixed_memory_window_config(CXLState *cxl_state,
fw->enc_int_gran = 0;
}
cxl_state->fixed_windows = g_list_append(cxl_state->fixed_windows, fw);
cxl_state->fixed_windows = g_list_append(cxl_state->fixed_windows,
g_steal_pointer(&fw));
return;
}
@ -103,7 +104,6 @@ static bool cxl_hdm_find_target(uint32_t *cache_mem, hwaddr addr,
uint32_t ctrl;
uint32_t ig_enc;
uint32_t iw_enc;
uint32_t target_reg;
uint32_t target_idx;
ctrl = cache_mem[R_CXL_HDM_DECODER0_CTRL];
@ -115,14 +115,13 @@ static bool cxl_hdm_find_target(uint32_t *cache_mem, hwaddr addr,
iw_enc = FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, IW);
target_idx = (addr / cxl_decode_ig(ig_enc)) % (1 << iw_enc);
if (target_idx > 4) {
target_reg = cache_mem[R_CXL_HDM_DECODER0_TARGET_LIST_LO];
target_reg >>= target_idx * 8;
if (target_idx < 4) {
*target = extract32(cache_mem[R_CXL_HDM_DECODER0_TARGET_LIST_LO],
target_idx * 8, 8);
} else {
target_reg = cache_mem[R_CXL_HDM_DECODER0_TARGET_LIST_LO];
target_reg >>= (target_idx - 4) * 8;
*target = extract32(cache_mem[R_CXL_HDM_DECODER0_TARGET_LIST_HI],
(target_idx - 4) * 8, 8);
}
*target = target_reg & 0xff;
return true;
}

4
hw/cxl/cxl-mailbox-utils.c
View File

@ -406,7 +406,7 @@ static struct cxl_cmd cxl_cmd_set[256][256] = {
cmd_identify_memory_device, 0, 0 },
[CCLS][GET_PARTITION_INFO] = { "CCLS_GET_PARTITION_INFO",
cmd_ccls_get_partition_info, 0, 0 },
[CCLS][GET_LSA] = { "CCLS_GET_LSA", cmd_ccls_get_lsa, 0, 0 },
[CCLS][GET_LSA] = { "CCLS_GET_LSA", cmd_ccls_get_lsa, 8, 0 },
[CCLS][SET_LSA] = { "CCLS_SET_LSA", cmd_ccls_set_lsa,
~0, IMMEDIATE_CONFIG_CHANGE | IMMEDIATE_DATA_CHANGE },
};
@ -425,7 +425,7 @@ void cxl_process_mailbox(CXLDeviceState *cxl_dstate)
cxl_cmd = &cxl_cmd_set[set][cmd];
h = cxl_cmd->handler;
if (h) {
if (len == cxl_cmd->in) {
if (len == cxl_cmd->in || cxl_cmd->in == ~0) {
cxl_cmd->payload = cxl_dstate->mbox_reg_state +
A_CXL_DEV_CMD_PAYLOAD;
ret = (*h)(cxl_cmd, cxl_dstate, &len);

2
hw/i386/microvm.c
View File

@ -332,7 +332,7 @@ static void microvm_memory_init(MicrovmMachineState *mms)
rom_set_fw(fw_cfg);
if (machine->kernel_filename != NULL) {
x86_load_linux(x86ms, fw_cfg, 0, true, false);
x86_load_linux(x86ms, fw_cfg, 0, true, true);
}
if (mms->option_roms) {

2
hw/i386/pc_piix.c
View File

@ -439,6 +439,7 @@ static void pc_i440fx_7_1_machine_options(MachineClass *m)
m->alias = "pc";
m->is_default = true;
pcmc->default_cpu_version = 1;
pcmc->legacy_no_rng_seed = true;
}
DEFINE_I440FX_MACHINE(v7_1, "pc-i440fx-7.1", NULL,
@ -450,7 +451,6 @@ static void pc_i440fx_7_0_machine_options(MachineClass *m)
pc_i440fx_7_1_machine_options(m);
m->alias = NULL;
m->is_default = false;
pcmc->legacy_no_rng_seed = true;
pcmc->enforce_amd_1tb_hole = false;
compat_props_add(m->compat_props, hw_compat_7_0, hw_compat_7_0_len);
compat_props_add(m->compat_props, pc_compat_7_0, pc_compat_7_0_len);

2
hw/i386/pc_q35.c
View File

@ -376,6 +376,7 @@ static void pc_q35_7_1_machine_options(MachineClass *m)
pc_q35_machine_options(m);
m->alias = "q35";
pcmc->default_cpu_version = 1;
pcmc->legacy_no_rng_seed = true;
}
DEFINE_Q35_MACHINE(v7_1, "pc-q35-7.1", NULL,
@ -386,7 +387,6 @@ static void pc_q35_7_0_machine_options(MachineClass *m)
PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
pc_q35_7_1_machine_options(m);
m->alias = NULL;
pcmc->legacy_no_rng_seed = true;
pcmc->enforce_amd_1tb_hole = false;
compat_props_add(m->compat_props, hw_compat_7_0, hw_compat_7_0_len);
compat_props_add(m->compat_props, pc_compat_7_0, pc_compat_7_0_len);

11
hw/scsi/virtio-scsi-dataplane.c
View File

@ -136,6 +136,14 @@ int virtio_scsi_dataplane_start(VirtIODevice *vdev)
memory_region_transaction_commit();
/*
* These fields are visible to the IOThread so we rely on implicit barriers
* in aio_context_acquire() on the write side and aio_notify_accept() on
* the read side.
*/
s->dataplane_starting = false;
s->dataplane_started = true;
aio_context_acquire(s->ctx);
virtio_queue_aio_attach_host_notifier(vs->ctrl_vq, s->ctx);
virtio_queue_aio_attach_host_notifier_no_poll(vs->event_vq, s->ctx);
@ -143,9 +151,6 @@ int virtio_scsi_dataplane_start(VirtIODevice *vdev)
for (i = 0; i < vs->conf.num_queues; i++) {
virtio_queue_aio_attach_host_notifier(vs->cmd_vqs[i], s->ctx);
}
s->dataplane_starting = false;
s->dataplane_started = true;
aio_context_release(s->ctx);
return 0;

4
hw/virtio/vhost-user.c
View File

@ -295,6 +295,8 @@ static int vhost_user_read_header(struct vhost_dev *dev, VhostUserMsg *msg)
return -EPROTO;
}
trace_vhost_user_read(msg->hdr.request, msg->hdr.flags);
return 0;
}
@ -544,8 +546,6 @@ static int vhost_user_set_log_base(struct vhost_dev *dev, uint64_t base,
}
}
trace_vhost_user_read(msg.hdr.request, msg.hdr.flags);
return 0;
}

10
hw/virtio/vhost.c
View File

@ -306,7 +306,7 @@ static inline void vhost_dev_log_resize(struct vhost_dev *dev, uint64_t size)
dev->log_size = size;
}
static int vhost_dev_has_iommu(struct vhost_dev *dev)
static bool vhost_dev_has_iommu(struct vhost_dev *dev)
{
VirtIODevice *vdev = dev->vdev;
@ -316,8 +316,12 @@ static int vhost_dev_has_iommu(struct vhost_dev *dev)
* does not have IOMMU, there's no need to enable this feature
* which may cause unnecessary IOTLB miss/update transactions.
*/
return virtio_bus_device_iommu_enabled(vdev) &&
virtio_host_has_feature(vdev, VIRTIO_F_IOMMU_PLATFORM);
if (vdev) {
return virtio_bus_device_iommu_enabled(vdev) &&
virtio_host_has_feature(vdev, VIRTIO_F_IOMMU_PLATFORM);
} else {
return false;
}
}
static void *vhost_memory_map(struct vhost_dev *dev, hwaddr addr,

19
hw/virtio/virtio-pci.c
View File

@ -996,9 +996,14 @@ static int virtio_pci_set_guest_notifiers(DeviceState *d, int nvqs, bool assign)
nvqs = MIN(nvqs, VIRTIO_QUEUE_MAX);
/* When deassigning, pass a consistent nvqs value
* to avoid leaking notifiers.
/*
* When deassigning, pass a consistent nvqs value to avoid leaking
* notifiers. But first check we've actually been configured, exit
* early if we haven't.
*/
if (!assign && !proxy->nvqs_with_notifiers) {
return 0;
}
assert(assign || nvqs == proxy->nvqs_with_notifiers);
proxy->nvqs_with_notifiers = nvqs;
@ -1942,7 +1947,6 @@ static void virtio_pci_reset(DeviceState *qdev)
{
VirtIOPCIProxy *proxy = VIRTIO_PCI(qdev);
VirtioBusState *bus = VIRTIO_BUS(&proxy->bus);
PCIDevice *dev = PCI_DEVICE(qdev);
int i;
virtio_bus_reset(bus);
@ -1955,6 +1959,13 @@ static void virtio_pci_reset(DeviceState *qdev)
proxy->vqs[i].avail[0] = proxy->vqs[i].avail[1] = 0;
proxy->vqs[i].used[0] = proxy->vqs[i].used[1] = 0;
}
}
static void virtio_pci_bus_reset(DeviceState *qdev)
{
PCIDevice *dev = PCI_DEVICE(qdev);
virtio_pci_reset(qdev);
if (pci_is_express(dev)) {
pcie_cap_deverr_reset(dev);
@ -2022,7 +2033,7 @@ static void virtio_pci_class_init(ObjectClass *klass, void *data)
k->class_id = PCI_CLASS_OTHERS;
device_class_set_parent_realize(dc, virtio_pci_dc_realize,
&vpciklass->parent_dc_realize);
dc->reset = virtio_pci_reset;
dc->reset = virtio_pci_bus_reset;
}
static const TypeInfo virtio_pci_info = {

4
tests/qtest/bios-tables-test.c
View File

@ -1632,7 +1632,9 @@ static void test_acpi_q35_applesmc(void)
.variant = ".applesmc",
};
test_acpi_one("-device isa-applesmc", &data);
/* supply fake 64-byte OSK to silence missing key warning */
test_acpi_one("-device isa-applesmc,osk=any64characterfakeoskisenough"
"topreventinvalidkeywarningsonstderr", &data);
free_test_data(&data);
}