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test: lm32: make test cases independent 

Make test cases independent from from each other. Eg. if a test case needs
a specific value in register A, don't rely on the fact that it is already
set by the preceding test case.

Signed-off-by: Michael Walle <michael@walle.cc>
This commit is contained in:
Michael Walle 2014-04-22 20:18:41 +02:00
parent 178ac111bc
commit a946ce8020
8 changed files with 25 additions and 0 deletions
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4
tests/tcg/lm32/test_lb.S
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@ -8,10 +8,12 @@ lb r3, (r1+0)
check_r3 0x7e check_r3 0x7e
test_name LB_2 test_name LB_2
load r1 data
lb r3, (r1+1) lb r3, (r1+1)
check_r3 0x7f check_r3 0x7f
test_name LB_3 test_name LB_3
load r1 data
lb r3, (r1+-1) lb r3, (r1+-1)
check_r3 0x7d check_r3 0x7d
@ -21,10 +23,12 @@ lb r3, (r1+0)
check_r3 0xfffffffe check_r3 0xfffffffe
test_name LB_5 test_name LB_5
load r1 data_msb
lb r3, (r1+1) lb r3, (r1+1)
check_r3 0xffffffff check_r3 0xffffffff
test_name LB_6 test_name LB_6
load r1 data_msb
lb r3, (r1+-1) lb r3, (r1+-1)
check_r3 0xfffffffd check_r3 0xfffffffd

4
tests/tcg/lm32/test_lbu.S
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@ -8,10 +8,12 @@ lbu r3, (r1+0)
check_r3 0x7e check_r3 0x7e
test_name LBU_2 test_name LBU_2
load r1 data
lbu r3, (r1+1) lbu r3, (r1+1)
check_r3 0x7f check_r3 0x7f
test_name LBU_3 test_name LBU_3
load r1 data
lbu r3, (r1+-1) lbu r3, (r1+-1)
check_r3 0x7d check_r3 0x7d
@ -21,10 +23,12 @@ lbu r3, (r1+0)
check_r3 0xfe check_r3 0xfe
test_name LBU_5 test_name LBU_5
load r1 data_msb
lbu r3, (r1+1) lbu r3, (r1+1)
check_r3 0xff check_r3 0xff
test_name LBU_6 test_name LBU_6
load r1 data_msb
lbu r3, (r1+-1) lbu r3, (r1+-1)
check_r3 0xfd check_r3 0xfd

4
tests/tcg/lm32/test_lh.S
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@ -8,10 +8,12 @@ lh r3, (r1+0)
check_r3 0x7e7f check_r3 0x7e7f
test_name LH_2 test_name LH_2
load r1 data
lh r3, (r1+2) lh r3, (r1+2)
check_r3 0x7071 check_r3 0x7071
test_name LH_3 test_name LH_3
load r1 data
lh r3, (r1+-2) lh r3, (r1+-2)
check_r3 0x7c7d check_r3 0x7c7d
@ -21,10 +23,12 @@ lh r3, (r1+0)
check_r3 0xfffffeff check_r3 0xfffffeff
test_name LH_5 test_name LH_5
load r1 data_msb
lh r3, (r1+2) lh r3, (r1+2)
check_r3 0xfffff0f1 check_r3 0xfffff0f1
test_name LH_6 test_name LH_6
load r1 data_msb
lh r3, (r1+-2) lh r3, (r1+-2)
check_r3 0xfffffcfd check_r3 0xfffffcfd

4
tests/tcg/lm32/test_lhu.S
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@ -8,10 +8,12 @@ lhu r3, (r1+0)
check_r3 0x7e7f check_r3 0x7e7f
test_name LHU_2 test_name LHU_2
load r1 data
lhu r3, (r1+2) lhu r3, (r1+2)
check_r3 0x7071 check_r3 0x7071
test_name LHU_3 test_name LHU_3
load r1 data
lhu r3, (r1+-2) lhu r3, (r1+-2)
check_r3 0x7c7d check_r3 0x7c7d
@ -21,10 +23,12 @@ lhu r3, (r1+0)
check_r3 0xfeff check_r3 0xfeff
test_name LHU_5 test_name LHU_5
load r1 data_msb
lhu r3, (r1+2) lhu r3, (r1+2)
check_r3 0xf0f1 check_r3 0xf0f1
test_name LHU_6 test_name LHU_6
load r1 data_msb
lhu r3, (r1+-2) lhu r3, (r1+-2)
check_r3 0xfcfd check_r3 0xfcfd

2
tests/tcg/lm32/test_lw.S
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@ -8,10 +8,12 @@ lw r3, (r1+0)
check_r3 0x7e7f7071 check_r3 0x7e7f7071
test_name LW_2 test_name LW_2
load r1 data
lw r3, (r1+4) lw r3, (r1+4)
check_r3 0x72737475 check_r3 0x72737475
test_name LW_3 test_name LW_3
load r1 data
lw r3, (r1+-4) lw r3, (r1+-4)
check_r3 0x7a7b7c7d check_r3 0x7a7b7c7d

2
tests/tcg/lm32/test_sb.S
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@ -9,11 +9,13 @@ sb (r1+0), r2
check_mem data 0xaa000000 check_mem data 0xaa000000
test_name SB_2 test_name SB_2
load r1 data
load r2 0xf0f1f2bb load r2 0xf0f1f2bb
sb (r1+1), r2 sb (r1+1), r2
check_mem data 0xaabb0000 check_mem data 0xaabb0000
test_name SB_3 test_name SB_3
load r1 data
load r2 0xf0f1f2cc load r2 0xf0f1f2cc
sb (r1+-1), r2 sb (r1+-1), r2
check_mem data0 0x000000cc check_mem data0 0x000000cc

2
tests/tcg/lm32/test_sh.S
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@ -9,11 +9,13 @@ sh (r1+0), r2
check_mem data 0xaaaa0000 check_mem data 0xaaaa0000
test_name SH_2 test_name SH_2
load r1 data
load r2 0xf0f1bbbb load r2 0xf0f1bbbb
sh (r1+2), r2 sh (r1+2), r2
check_mem data 0xaaaabbbb check_mem data 0xaaaabbbb
test_name SH_3 test_name SH_3
load r1 data
load r2 0xf0f1cccc load r2 0xf0f1cccc
sh (r1+-2), r2 sh (r1+-2), r2
check_mem data0 0x0000cccc check_mem data0 0x0000cccc

3
tests/tcg/lm32/test_sw.S
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@ -9,16 +9,19 @@ sw (r1+0), r2
check_mem data 0xaabbccdd check_mem data 0xaabbccdd
test_name SW_2 test_name SW_2
load r1 data
load r2 0x00112233 load r2 0x00112233
sw (r1+4), r2 sw (r1+4), r2
check_mem data1 0x00112233 check_mem data1 0x00112233
test_name SW_3 test_name SW_3
load r1 data
load r2 0x44556677 load r2 0x44556677
sw (r1+-4), r2 sw (r1+-4), r2
check_mem data0 0x44556677 check_mem data0 0x44556677
test_name SW_4 test_name SW_4
load r1 data
sw (r1+0), r1 sw (r1+0), r1
lw r3, (r1+0) lw r3, (r1+0)
check_r3 data check_r3 data