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target/loongarch: Implement vsadd/vssub 

This patch includes:
- VSADD.{B/H/W/D}[U];
- VSSUB.{B/H/W/D}[U].

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-8-gaosong@loongson.cn>
This commit is contained in:
Song Gao 2023-05-04 20:27:33 +08:00
parent be9ec55758
commit a94cb91107
No known key found for this signature in database
GPG Key ID: 40A2FFF239263EDF
3 changed files with 51 additions and 0 deletions
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17
target/loongarch/disas.c
View File

@ -831,3 +831,20 @@ INSN_LSX(vneg_b, vv)
INSN_LSX(vneg_h, vv)
INSN_LSX(vneg_w, vv)
INSN_LSX(vneg_d, vv)
INSN_LSX(vsadd_b, vvv)
INSN_LSX(vsadd_h, vvv)
INSN_LSX(vsadd_w, vvv)
INSN_LSX(vsadd_d, vvv)
INSN_LSX(vsadd_bu, vvv)
INSN_LSX(vsadd_hu, vvv)
INSN_LSX(vsadd_wu, vvv)
INSN_LSX(vsadd_du, vvv)
INSN_LSX(vssub_b, vvv)
INSN_LSX(vssub_h, vvv)
INSN_LSX(vssub_w, vvv)
INSN_LSX(vssub_d, vvv)
INSN_LSX(vssub_bu, vvv)
INSN_LSX(vssub_hu, vvv)
INSN_LSX(vssub_wu, vvv)
INSN_LSX(vssub_du, vvv)

17
target/loongarch/insn_trans/trans_lsx.c.inc
View File

@ -140,3 +140,20 @@ TRANS(vneg_b, gvec_vv, MO_8, tcg_gen_gvec_neg)
TRANS(vneg_h, gvec_vv, MO_16, tcg_gen_gvec_neg)
TRANS(vneg_w, gvec_vv, MO_32, tcg_gen_gvec_neg)
TRANS(vneg_d, gvec_vv, MO_64, tcg_gen_gvec_neg)
TRANS(vsadd_b, gvec_vvv, MO_8, tcg_gen_gvec_ssadd)
TRANS(vsadd_h, gvec_vvv, MO_16, tcg_gen_gvec_ssadd)
TRANS(vsadd_w, gvec_vvv, MO_32, tcg_gen_gvec_ssadd)
TRANS(vsadd_d, gvec_vvv, MO_64, tcg_gen_gvec_ssadd)
TRANS(vsadd_bu, gvec_vvv, MO_8, tcg_gen_gvec_usadd)
TRANS(vsadd_hu, gvec_vvv, MO_16, tcg_gen_gvec_usadd)
TRANS(vsadd_wu, gvec_vvv, MO_32, tcg_gen_gvec_usadd)
TRANS(vsadd_du, gvec_vvv, MO_64, tcg_gen_gvec_usadd)
TRANS(vssub_b, gvec_vvv, MO_8, tcg_gen_gvec_sssub)
TRANS(vssub_h, gvec_vvv, MO_16, tcg_gen_gvec_sssub)
TRANS(vssub_w, gvec_vvv, MO_32, tcg_gen_gvec_sssub)
TRANS(vssub_d, gvec_vvv, MO_64, tcg_gen_gvec_sssub)
TRANS(vssub_bu, gvec_vvv, MO_8, tcg_gen_gvec_ussub)
TRANS(vssub_hu, gvec_vvv, MO_16, tcg_gen_gvec_ussub)
TRANS(vssub_wu, gvec_vvv, MO_32, tcg_gen_gvec_ussub)
TRANS(vssub_du, gvec_vvv, MO_64, tcg_gen_gvec_ussub)

17
target/loongarch/insns.decode
View File

@ -525,3 +525,20 @@ vneg_b 0111 00101001 11000 01100 ..... ..... @vv
vneg_h 0111 00101001 11000 01101 ..... ..... @vv
vneg_w 0111 00101001 11000 01110 ..... ..... @vv
vneg_d 0111 00101001 11000 01111 ..... ..... @vv
vsadd_b 0111 00000100 01100 ..... ..... ..... @vvv
vsadd_h 0111 00000100 01101 ..... ..... ..... @vvv
vsadd_w 0111 00000100 01110 ..... ..... ..... @vvv
vsadd_d 0111 00000100 01111 ..... ..... ..... @vvv
vsadd_bu 0111 00000100 10100 ..... ..... ..... @vvv
vsadd_hu 0111 00000100 10101 ..... ..... ..... @vvv
vsadd_wu 0111 00000100 10110 ..... ..... ..... @vvv
vsadd_du 0111 00000100 10111 ..... ..... ..... @vvv
vssub_b 0111 00000100 10000 ..... ..... ..... @vvv
vssub_h 0111 00000100 10001 ..... ..... ..... @vvv
vssub_w 0111 00000100 10010 ..... ..... ..... @vvv
vssub_d 0111 00000100 10011 ..... ..... ..... @vvv
vssub_bu 0111 00000100 11000 ..... ..... ..... @vvv
vssub_hu 0111 00000100 11001 ..... ..... ..... @vvv
vssub_wu 0111 00000100 11010 ..... ..... ..... @vvv
vssub_du 0111 00000100 11011 ..... ..... ..... @vvv